Abstract-Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge loss remain the challenging issues for charge trap Flash (CTF) memories. In this paper, the dependence of SANOS memory performance and reliability on the composition of silicon nitride (SiN) layer is extensively studied. The effect of varying the Si:N ratio on program (P)/E and retention characteristics is investigated. SiN composition is shown to significantly alter the electron and hole trap properties. Varying the SiN composition from N-rich (N + ) to Si-rich (Si + ) lowers electron trap depth but increases hole trap depth, causing lower P state saturation but significant overerase, resulting in an enhanced memory window. During retention, P state charge loss depends on thermal emission followed by the tunneling out of electrons mostly through tunnel dielectric, which becomes worse for Si + SiN. Erase state charge loss mainly depends on hole redistribution under the influence of internal electric fields, which improves with Si + SiN. This paper identifies several important performances versus reliability tradeoffs to be considered during the optimization of SiN layer composition. It also explores the option for CTF optimization through the engineering of SiN stoichiometry for multilevel cell NAND Flash applications.Index Terms-Charge trap Flash (CTF), program/erase (P/E) window, retention, SANOS, silicon nitride (SiN), SONOS.

Abstract-Program/Erase (P/E) cycling endurance in poly-Si/Al 2 O 3 /SiN/SiO 2 /Si (SANOS) memories is systematically studied. Cycling-induced trap generation, memory window (MW) closure, and eventual stack breakdown are shown to be strongly influenced by the material composition of the silicon nitride (SiN) charge trap layer. P/E pulsewidth and amplitude, as well as starting program and erase flatband voltage (V FB ) levels (therefore the overall MW), are shown to uniquely impact stack degradation and breakdown. An electron-flux-driven anode hole generation model is proposed, and trap generation in both SiN and tunnel oxide are used to explain stack degradation and breakdown. This paper emphasizes the importance of SiN layer optimization for reliably sustaining large MW during P/E operation of SANOS memories.