Characterization of the V/sub T/-instability in SiO/sub 2//HfO/sub 2/ gate dielectrics

Abstract

The electrical stability of CMOS devices with conventional gate dielectrics is commonly studied using static (DC) measurement techniques. By applying the same methods to MOS devices with alternative gate dielectrics, it has been shown that alternative gate stacks suffer from severe charge trapping and that the trapped charge is not stable, leading to fast transient charging components. In this paper timeresolved measurement techniques down to the p time range are applied to capture the fast transient component of the charge trapping observed in SiO, I Hf02 dual layer gate stacks. Furthermore, its impact on the device performance and reliability of n-channel FETs is discussed.

The Pulsed Id-Vgmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

“…1) [74], where the trapping may occur within hundreds of nanoseconds to microseconds [50,73]. The charges trapped during this process are well-localized within the dielectric, with their spatial distribution through the dielectric thickness being determined by the Fermi energy of the channel electrons and the trap energy (presumably, a neutral or singlecharged negative oxygen vacancies) [4,7,[9][10][11]16] fast trapping, which is reversible with no residual damage [30,75,76], can contribute significantly to threshold voltage (V t ) instability and degradation of device performance in Hf-based gate stack nMOS transistors. pMOS Hf-based transistors, on the other hand, typically exhibit negligible fast transient charging (FTC) [33,77] in inversion due to a lack of defect states with the appropriate energies.…”

“…While significant progress has been made in fabricating high-κ gate stacks with less charge trapping [66][67][68][69], pulse-based characterization techniques [30,[70][71][72][73] remain critically important in understanding charge trapping processes for low power applications, memory cells, etc. This review addresses pulsed currentvoltage (I-V) characterization and analysis approaches.…”

Charge trapping in ultrathin hafnium silicate/metal gate stacks

“…1(a)]. The electron trapping rate increases as the slope of the threshold voltage shift also increases with the applied stress time [6]. Curve fit of the data was done using the equation [3] where is proportional to total trap density and are model parameters [8].…”

“…n-MOSFETs with were considered for stress, which were performed on fresh devices with uniform threshold voltages. Constant voltage stress (CVS) was applied with gate bias 1, 1.5, 2, and 3 V while constant current stress (CCS) [6] with current densities of 2, 4, 10, and 20 A/cm ( 50, 100, 250, and 500 nA) were applied at the gate using a semi-automated test measurement setup with HP4156 semiconductor parameter analyzer controlled by a LabVIEW program.…”

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

“…Evidence of the presence of border traps can also be observed in an I d -V g characteristic, where it is manifest as a hysteresis loop. 22 A single triangular pulse I d -V g hysteresis, 23 performed at V ds ¼ 50 mV and t r ¼ t f ¼ 500 ns, is shown in (Fig. 2).…”