The Pulsed I<sub>d</sub>-V<sub>g</sub>methodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Young, Chadwin D.; Heh, D.; Choi, Rino; Lee, Byoung Hun; Bersuker, G.

doi:10.5573/jsts.2010.10.2.079

Cited by 24 publications

(17 citation statements)

References 89 publications

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“…Because of the intrinsic n-type nature of MoS 2 , electrons in the MoS 2 channel will be close to the Al 2 O 3 /MoS 2 interface when V bg is negative and will move nearer to the SiO 2 /MoS 2 interface for positive V bg . Δ I d is proportional to the magnitude of traps . Hence, the change in Δ I d shows that there are fewer traps in the Al 2 O 3 /MoS 2 interface, indicating a better interface quality compared to that of SiO 2 /MoS 2 interface.…”

Section: Resultsmentioning

confidence: 99%

“…It is well known that conventional direct current (DC) characterization methods have charge trapping phenomena that occur during long measurements . To minimize the effect of charge trapping and detrapping, pulsed IV measurement is required to obtain the intrinsic electrical characteristics of the MoS 2 transistors. , DC I d is compared with I d measured using different pulse widths, as V d is swept from 0 to 3.5 V with V bg = −30 V at 300 K as shown in Figure a. The pulse width is changed from 5 ms (blue) to 25 ms (magenta).…”

Section: Resultsmentioning

confidence: 99%

“…Similar to the case in (a), all pulsed curves are higher than the DC curves. The more traps in the interface, the more drain current degradation Δ I d . To investigate the interface quality, we define Δ I d as the difference between the DC and the pulse measurements with 5 ms pulse width at V d = 2 V. Figure c shows Δ I d versus V bg with various V tg values at 300 K. It is apparent that Δ I d increases with increasing V bg , and the trend is independent of V tg.…”

Section: Resultsmentioning

confidence: 99%

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Effect of Dielectric Interface on the Performance of MoS₂ Transistors

Xiong

et al. 2017

ACS Appl. Mater. Interfaces

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Because of their wide bandgap and ultrathin body properties, two-dimensional materials are currently being pursued for next-generation electronic and optoelectronic applications. Although there have been increasing numbers of studies on improving the performance of MoS field-effect transistors (FETs) using various methods, the dielectric interface, which plays a decisive role in determining the mobility, interface traps, and thermal transport of MoS FETs, has not been well explored and understood. In this article, we present a comprehensive experimental study on the effect of high-k dielectrics on the performance of few-layer MoS FETs from 300 to 4.3 K. Results show that AlO/HfO could boost the mobility and drain current. Meanwhile, MoS transistors with AlO/HfO demonstrate a 2× reduction in oxide trap density compared to that of the devices with the conventional SiO substrate. Also, we observe a negative differential resistance effect on the device with 1 μm-channel length when using conventional SiO as the gate dielectric due to self-heating, and this is effectively eliminated by using the AlO/HfO gate dielectric. This dielectric engineering provides a highly viable route to realizing high-performance transition metal dichalcogenide-based FETs.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

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Effect of Dielectric Interface on the Performance of MoS₂ Transistors

Xiong

et al. 2017

ACS Appl. Mater. Interfaces

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“…In our work, we aim to understand defects and investigate both their impact on device performance and the transient charge trapping characteristics of dual active-layer TFTs with HfInZnO (HIZO) front channels and InZnO (IZO) back channels using pulse I–V measurements, and provide an accurate method for determining mobility in an environment with minimal charge trapping 42–46 . To this end, we employed microsecond fast ramp I–V (μs-FIV), pulse I–V (PIV), the transient current method, and discharge current analysis (DCA).…”

Section: Introductionmentioning

confidence: 99%

Microsecond Pulse I–V Approach to Understanding Defects in High Mobility Bi-layer Oxide Semiconductor Transistor

Woo

Jeon

2017

Sci Rep

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The carrier transport and device instability of amorphous oxide semiconductor devices are influenced by defects that are exponentially distributed in energy, because of amorphous phase channels and front/back interfaces with a large number of sub-gap states. Thus, understanding defects and charge trapping in oxide semiconductor transistors is required for being core device element in reliable production lines. In this paper, we present the transient charging effect, the charge trapping mechanism, and the dynamic charge transport of high-mobility bilayer oxide semiconductor transistors. To this end, we exploited microsecond ramps, pulse ID–VG, transient current, and discharge current analysis methods. The mobility enhancement rate of single HfInZnO (HIZO) and bilayer HfInZnO-InZnO (HIZO-IZO) were 173.8 and 28.8%, respectively, in the charge-trapping-free environment. Transient charge trapping can be classified to temperature insensitive fast charging and thermally activated slow charging with two different trap energies. Insignificant fast transient charging of a bilayer-oxide high-mobility thin film transistor(TFT) can be explained by the low density of sub-gap states in the oxide semiconductor. Understanding defects and transient charging in the oxide semiconductor helps to determine the origin of device instability of oxide TFTs, and finally, to solve this problem.

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“…Accurate time-domain device characterizations in the range from ns to µs are essential toward building accurate device models as well as tracking a wealth of reliability concerns [6][7][8][9] spanning charge trapping to self-heating. When designing analog circuits like the DC converters, ADC/DAC and low noise amplifiers used for signal detection in quantum computers, accuracy of the modeling parameters such as the threshold voltage, capacitance, mobility etc.…”

Section: Introductionmentioning

confidence: 99%

Ultrafast I_D – V_G Technique for Reliable Cryogenic Device Characterization

Shrestha

Akturk

Hoskins

et al. 2023

IEEE J. Electron Devices Soc.

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An in-depth understanding of the transient operation of devices at cryogenic temperatures remains experimentally elusive. However, the impact of these transients has recently become important in efforts to develop both electronics to support quantum information science as well as cryogenic highperformance computing. In this paper, we discuss a fast timedependent device characterization technique, capable of examining the charge trapping dynamics of devices operating at cryogenic temperatures. Careful calibrations allow for the acquisition of accurate fast I-V and transconductance transients down to 20 ns for devices operating down to 8 K. The trap charging dynamics was monitored via shifts in both threshold voltage and transconductance. The combination of fast measurements and cold temperatures were used to shift the observable measurement window to reveal charge trapping/de-trapping time dynamics of both fast and slow traps in high-k devices to demonstrate the utility of the fast I-V for cryogenic device characterization.

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The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Cited by 24 publications

References 89 publications

Effect of Dielectric Interface on the Performance of MoS₂ Transistors

Effect of Dielectric Interface on the Performance of MoS₂ Transistors

Microsecond Pulse I–V Approach to Understanding Defects in High Mobility Bi-layer Oxide Semiconductor Transistor

Ultrafast I_D – V_G Technique for Reliable Cryogenic Device Characterization

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The Pulsed Id-Vgmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Cited by 24 publications

References 89 publications

Effect of Dielectric Interface on the Performance of MoS2 Transistors

Effect of Dielectric Interface on the Performance of MoS2 Transistors

Microsecond Pulse I–V Approach to Understanding Defects in High Mobility Bi-layer Oxide Semiconductor Transistor

Ultrafast ID – VG Technique for Reliable Cryogenic Device Characterization

Contact Info

Product

Resources

About

The Pulsed I_d-V_gmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Effect of Dielectric Interface on the Performance of MoS₂ Transistors

Effect of Dielectric Interface on the Performance of MoS₂ Transistors

Ultrafast I_D – V_G Technique for Reliable Cryogenic Device Characterization