In this letter, we report for the first time a distinctive approach of implementing a junctionless transistor (JLT) without doping (doping-less) the ultrathin silicon film. A charge-plasma concept is employed to induce n-region for the formation of source and drain for a n-channel JLT using appropriate metal work function electrodes. Electrical characteristics of the proposed device are simulated and compared with that of a conventionally doped JLT of identical dimensions. In conventional JLTs, the channel doping concentration is generally kept high to ensure high ON-state current, but it causes variation in threshold voltage, which may be due to process variations. The proposed device solves the problem of threshold voltage variability without affecting inherent advantages of JLTs.
Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6T SRAM cells. To overcome this limitation, 7T SRAM designs were proposed earlier at the cost of extra silicon area. In this paper, we propose a novel 6T SRAM design using Si-TFETs for reliable operation with low leakage at ultra low voltages. We also demonstrate that a functional 6T TFET SRAM design with comparable stability margins and faster performances at low voltages can be realized using proposed design when compared with the 7T TFET SRAM cell. We achieve a leakage reduction improvement of 700X and 1600X over traditional CMOS SRAM designs at V DD of 0.3V and 0.5V respectively which makes it suitable for use at ultra-low power applications.
Power management and charging of batteries for wireless sensors become a problem when using them in the field applications. In this paper, we present RF energy harvesting circuit with three different approaches: resonator, number of multiplier stages and low pass filter (LPF). Resonator provide 30 times improvement in amplitude of input (100 mV) AC signal. In proposed circuit L type network, between input power source and rectifier, works as resonator as well as matching network at resonant frequency. It results in maximum efficiency 79% with 50kΩ load at -10 dBm input power. We also present the effect of multiplier stages on output voltage and RF to DC conversion efficiency. Optimum efficiency of approximately 80% is achieved with Dickson topology in input power region 0 to 10dBm for 3 rd , 5 th and 7 th stages, respectively. Application of LPF is also introduced with an existing circuit. It provides 140 mV improvement in output voltage with input power -10dBm. It also shows that maximum efficiency 75% and 64% is possible with dielectric constant ( r =9) and substrate height (H=0.0004m), for microstrip line of matching circuit at -10 dBm input power with 10 kΩ load.
In this paper, we report the potential benefits of dopingless double-gate field-effect transistor (DL-DGFET) designed on ultrathin silicon on insulator film for low power applications. The simulation results show that the proposed device exhibits higher ON current and less sensitivity toward device parameter variation compared with highly doped junctionless (JL) DGFET. The constraints of high metal gate workfunction of JL device are also relaxed using midgap materials as a gate electrode in the DL-DGFETs. Sensitivity analysis shows that the DL-DGFET exhibits least sensitivity to device parameter variation especially gate length due to suppression of short-channel effects. The DL-DGFET also shows lower static power dissipation in OFF state and lower intrinsic delay in ON state. The mixed-mode simulation of 6T-static random access memory cell using DL-DGFET shows impressive read and hold noise margins of 147 and 352 mV at V DD = 0.8 V for ultralow power applications. The possible fabrication process flow of DL-DGFET is also proposed.
Abstract:In this paper, we present a novel six-transistor (6T) single-ended static random access memory (SE-SRAM) cell for ultralow-voltage applications. The proposed design has a strong 2.65X worst case read static noise margin (SNM) compared to a standard 6T SRAM. A strong write-ability of logic 'one' is achieved, which is problematic in an SE-SRAM cell with a 36% improvement compared to standard 6T SRAMs. A 16 × 16 × 32 bit SRAM with proposed and standard 6T bitcells is simulated and evaluated for read SNM, write-ability and power. The dynamic and leakage power dissipation in the proposed 6T SRAM are reduced by 28% and 21%, respectively, as compared to standard 6T SRAM.
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