A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications

Singh, Jawar; Ramakrishnan, K. K.; Mookerjea, S.; Datta, Suman; Narayanan, Vijaykrishnan; Pradhan, Dhiraj K.

doi:10.1109/aspdac.2010.5419897

Cited by 72 publications

(45 citation statements)

References 12 publications

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“…To perform circuit simulations, we capture the I d -V g transfer characteristics of the CMOS and the HTFET obtained using the models discussed in section II-A, in a Verilog-A lookup table [14], [15], [16]. Because of delayed onset of saturation in the HTFET, the Voltage Transfer Characteristics (VTC) of a HTFET inverter are considerably degraded compared to that of a CMOS inverter, as shown in Fig.…”

Section: A Tfet and Cmos Device Modelsmentioning

confidence: 99%

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Saripalli

Datta

Narayanan

et al. 2011

2011 IEEE/ACM International Symposium on Nanoscale Architectures

119

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Abstract-Steep sub-threshold Interband Tunnel FETs (TFETs) are promising candidates for low supply voltage applications with higher switching performance than traditional CMOS. Unlike CMOS, TFETs exhibit uni-directional conduction due to their asymmetric source-drain architecture, and delayed output saturation characteristics. These unconventional characteristics of TFETs pose a challenge for providing good read/write noise margin characteristics in TFET SRAMs. We provide an analysis of 8T and 10T TFET SRAM cells, including Schmitt-Trigger (ST) based cells, to address these shortcomings. By benchmarking a variety of TFET-based SRAM cells, we show the utility of the Schmitt-Trigger feedback mechanism in improving the read/write noise margins, thus enabling ultra low-VCC operation for TFET SRAMs. We also propose a variation model for studying the impact of device-level variation on TFET SRAM cells. We show that the TFET ST SRAM cell has sufficient variation tolerance to operate at low-VCC, and is a very promising cell to achieve a VCC-min of 124mV. The TFET ST cell operating at its VCC-min provides a 1.2x reduction in dynamic energy and 13x reduction in leakage power compared to the best CMOS-based SRAM implementation operating at it's VCC-min, while giving better performance at the same time.

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Section: A Tfet and Cmos Device Modelsmentioning

confidence: 99%

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Saripalli

Datta

Narayanan

et al. 2011

2011 IEEE/ACM International Symposium on Nanoscale Architectures

119

View full text Add to dashboard Cite

show abstract

“…A table look up model approach is used for TFET circuit simulation due to the unavailability of physics based compact analytical model for TFET. The circuit simulations on commercial device simulators does not work properly for TFET based complementary circuits [33], and an equivalent circuit [34] or a table look up model based approach is required to perform logic circuit analysis. This tool has already been used to study the device and circuit performance of carbon nanotube p-i-n TFET [35].…”

Section: Circuit Level Performance Comparisonmentioning

confidence: 99%

Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric

Narang¹,

Saxena²,

Gupta³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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“…By comparing those designs on several aspects (e.g. frequency, noise margins, power, and area), in this study, we apply the 6T TFET SRAM proposed by Singh et al [14] to implement the TFET-based register files.…”

Section: 2tunneling Field Effect Transistors (Tfets)mentioning

confidence: 99%

“…Recently, many different TFET SRAMs have been explored to overcome this limitation [14][15][16][17]. By comparing those designs on several aspects (e.g.…”

Section: 2tunneling Field Effect Transistors (Tfets)mentioning

confidence: 99%

Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Tan

2013

International Symposium on Quality Electronic Design (ISQED)

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State-of-the-art General-Purpose computing on Graphics Processing Unit (GPGPU) is facing severe power challenge due to the increasing number of cores placed on a chip with decreasing feature size. In order to hide the long latency operations, GPGPU employs the fine-grained multithreading among numerous active threads, leading to the sizeable register files with massive power consumption. Exploring the optimal power savings in register files becomes the critical and first step towards the energyefficient GPGPUs. The conventional method to reduce dynamic power consumption is the supply voltage scaling, and the inter-bank tunneling FETs (TFETs) are the promising candidates compared to CMOS for low voltage operations regarding to both leakage and performance. However, always executing at the low voltage (so that low frequency) will result in significant performance degradation. In this study, we propose the hybrid CMOS-TFET based register files. To optimize the register power consumption, we allocate TFET-based registers to threads whose execution progress can be delayed to some degree to avoid the memory contentions with other threads, and the CMOS-based registers are still used for threads requiring normal execution speed. Our experimental results show that the proposed technique achieves 30% energy (including both dynamic and leakage) reduction in register files with little performance degradation compared to the baseline case equipped with naive power optimization technique.

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A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications

Cited by 72 publications

References 12 publications

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric

Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

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