Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric

“…Introducing a pocket(N+) near the Source(S)-Channel interface helps in reducing the tunneling width. The band is bent further at source junction because of pocketing in p-n-p-n con guration DLVNWTFET resulting in lowering of tunnel width, resulting in an increase in tunneling probability at the interface of Source(S) and Channel, hence improving the device performance [11].…”

Section: Ac and DC Performance Analysismentioning

confidence: 99%

Design and Performance Enhancement of Gate-on-Source PNPN Doping–Less Vertical Nanowire TFET

Lal

Verma

Kumar

et al. 2021

Silicon

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This paper outlines the study of a Doping-Less Vertical Nanowire Tunnel Field Effect Transistor (DLVNWTFET) with a p-i-n structure, aiming to enhance the performance of this device. The proposed device, which is a p-n-p-n con gured DLVNWTFET, switches with a steeper sub-threshold slope while keeping the Off-state current (I OFF ) and threshold-voltage (V TH ) low and also improves the On-state current (I ON ) of the device; which is one of the crucial problems in TFETs. The nanowire TFET structure is vertically grown on an intrinsic silicon wafer. This vertical structure eases the fabrication process and also helps in the implementation of Charge-Plasma (CP) Technique. It is a process by which electrodes of speci c work functions are used to induce charges in the Source (P) and Drain (N) regions. To realize the p-n-p-n con gured structure, pocketing technique is used where the N+ heavily doped pocket is introduced between the Source and the Channel through CP concept. Upon calculation and comparison of various analog and device parameters, the proposed p-n-p-n structure shows better performance in contrast to the p-i-n DLVNWTFET. Analysis of the performance of the two con gurations has been done, comparing various parameters like transconductance (G m ), output conductance (G D ), transfer characteristics (I D -V GS ), output characteristics (I D -V DS ), cut-off frequency (fT), total gate capacitance (C GG ) and intrinsic gain.

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“…TFETs and MOSFET of dual gate (DG) structures with a Gate length (L g ) of 30 nm, 1 nm thick HfO 2 and body thickness ( ) of 7 nm are simulated to investigate the energy band diagrams, I/C-V and SS. The achieved data is used to generate look up table based model for the circuit simulation using Verilog-A module in cadence spectre [8]. Fig.…”

Section: Carrier Injection Mechanism For Tfet and Mosfetmentioning

confidence: 99%

Impact of band to band Tunneling on Transient performance of Dual Gate Tunnel Field Effect Transistor (TFET)

Kumar¹,

Mishra²,

Mishra³

et al. 2019

IJITEE

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Tunnel Field Effect Transistor (TFET) is gated reverse biased P-I-N diode structured semiconductor device and can be considered as a reliable low power device. TCAD (Sentaurus 2D) simulations for various Gate metal work function (4.1-4.3 eV) shows that its ON-current (ION) arises from quantum mechanical band-to-band tunneling (B2BT) and observed that threshold Voltage (VT) for TFET decreases with increase in Gate metal work function. The thermionic emission of electrons in MOSFET limits the sub-threshold swing (SS) by 60 mV/dec whereas TFET has potential for low SS ie. SS<60 mV/dec. TCAD Simulations confirmed that that the Gate – Drain capacitance (Cgd) strongly follows the Gate capacitance (Cgg) all over the voltage range (0-0.9V) which increases the miller capacitance for TFET. It is investigated that for TFET, the injection of carriers into the channel is through B2BT which effectively couples the Gate charge to the Drain. A look up table based Verilog-A model is generated for TFET and used to simulate the static and dynamic behavior of TFET based digital circuit in Cadence spectre. Miller effect causes the peak voltage overshoots are noticed at the drain side during transient responses and can be responsible for dynamic power loss and high turn ON/OFF delay

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Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric

Abstract: Abstract-This work presents a comparative study of four Double Gate tunnel FET (DG-

Cited by 37 publications

References 33 publications

Electrical noise in Circular Gate Tunnel FET in presence of interface traps

Electrical noise in Circular Gate Tunnel FET in presence of interface traps

Design and Performance Enhancement of Gate-on-Source PNPN Doping–Less Vertical Nanowire TFET

Impact of band to band Tunneling on Transient performance of Dual Gate Tunnel Field Effect Transistor (TFET)

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