Electrical noise in Circular Gate Tunnel FET in presence of interface traps

Goswami, Rupam; Bhowmick, Brinda; Baishya, Srimanta

doi:10.1016/j.spmi.2015.07.064

Cited by 51 publications

(12 citation statements)

References 28 publications

(34 reference statements)

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“…This gate engineering introduces flexibility into the architecture of the device, and aids in optimization of chief electrical parameters, primarily the ambipolar current and ratio of on and off currents [53]. One of the techniques of reducing ambipolar current in a TFET apart from asymmetric source-drain doping is the introduction of gate-drain underlap [3,45,53]. In case of Circular Gate TFET, the gate being circular in shape, the gate dielectric thickness is dependent on the radius of the circle.…”

Section: A Circular Gate Tfet As a Dm Biosensormentioning

confidence: 99%

Dielectric-Modulated TFETs as Label-Free Biosensors

Goswami¹,

Bhowmick²

2018

Design, Simulation and Construction of Field Effect Transistors

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This chapter presents tunnel field effect transistors (TFETs) as dielectric-modulated (DM) label-free biosensors, and discusses various aspects related to them. A brief survey of the dielectric-modulated TFET biosensors is presented. The concept of dielectric modulation in TFETs is discussed with focus on principle and design perspectives. A Technology Computer Aided Design (TCAD) based approach to incorporate embedded nanogaps in TFET geometries along with appropriate physics-based simulation models are mentioned. Non-ideal conditions in dielectric-modulated biosensors are brought to light, keeping in view the practical considerations of the devices. A gate engineered TFET is taken up for analysis of sensitivities under different conditions through TCAD simulations. Finally, a status map of the sensitivities of the most significant works in dielectric-modulated label-free biosensors is depicted, and the status of the proposed TFET is highlighted.

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Section: A Circular Gate Tfet As a Dm Biosensormentioning

confidence: 99%

Dielectric-Modulated TFETs as Label-Free Biosensors

Goswami¹,

Bhowmick²

2018

Design, Simulation and Construction of Field Effect Transistors

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“…It is necessary to ensure that the device characteristics are less dependent on oxide-semiconductor interface traps. There are many reports on the effects of interface traps on the device performance of a TFET [24]. In general, the interface trap charges play a crucial role in affecting the threshold voltage of the device, which may deteriorate the performance of the device.…”

Section: Introductionmentioning

confidence: 99%

Role of gate electrode in influencing interface trap sensitivity in SOI tunnel FETs

Deb¹,

Goswami²,

Baruah³

et al. 2022

J. Micromech. Microeng.

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This article reports the response of a silicon-on-insulator (SOI) TFET to the presence of semiconductor/ gate dielectric interface traps. A systematic strategy is designed keeping in view different parameters which are related to the gate of the device. Acceptor-like traps, and donor-like traps with Gaussian distribution are considered at the said interface for the entire analysis. Sensitivity % is taken as a figure of merit which measures the deviation of the drain current in presence of traps from the cases with no traps. The effect of temperature on interface traps, and the effect of interface traps on gate leakage current are analyzed. The acceptor-like traps are found to affect the on-state regime, and the donor-like traps are found to affect the ambipolar regime. Analyses on gate-drain underlap, gate-source overlap, shift of entire gate over the device, and gate work-function suggest that the gate electrode plays an important role in determining the sensitivity of the TFETs. Furthermore, noise spectral densities in presence of flicker, diffusion, and monopolar generation-recombination noise sources, and interface traps are reported.

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“…One of the foremost disadvantage of TFET is its low ON state current [4][5]. Various research have been presented through structural engineering to enhanced the ON current of TFET like silicon on insulator (SOI) TFET [6], heterojunction TFET (HJ-TFET) [7], circular gate TFET (CG-TFET) [8], double gate (DG) TFET [9], dual material gate (DMG) TFET [10] and many more. Also, epitaxial layer (ETL) based TFET architecture is proposed to make TFET suitable for low power applications [11][12].…”

Section: Introductionmentioning

confidence: 99%

Performance Evaluation of Epitaxial Layer Based Gate Modulated TFET (GM-TFET)

Saha

Goswami

Bhowmick

et al. 2021

Silicon

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This paper reports the performance of an epitaxial layer (ETL) based gate modulated (GM-TFET) through 3D Technology Computer Aided Design (TCAD) simulations. The architecture utilizes effects of both vertical tunneling and lateral tunneling phenomena to improve the device performance. Attributes of the ETL, its thickness (t epi ) and doping concentration (N epi ) are varied and their impact on device electrical parameters such as transfer characteristic, output performance, subthreshold swing (SS), and threshold voltage (V T ) is highlighted. It is observed that both t epi and N epi significantly influence the different electrical parameters of the ETL based TFET architecture.

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Electrical noise in Circular Gate Tunnel FET in presence of interface traps

Cited by 51 publications

References 28 publications

Dielectric-Modulated TFETs as Label-Free Biosensors

Dielectric-Modulated TFETs as Label-Free Biosensors

Role of gate electrode in influencing interface trap sensitivity in SOI tunnel FETs

Performance Evaluation of Epitaxial Layer Based Gate Modulated TFET (GM-TFET)

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