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Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6T SRAM cells. To overcome this limitation, 7T SRAM designs were proposed earlier at the cost of extra silicon area. In this paper, we propose a novel 6T SRAM design using Si-TFETs for reliable operation with low leakage at ultra low voltages. We also demonstrate that a functional 6T TFET SRAM design with comparable stability margins and faster performances at low voltages can be realized using proposed design when compared with the 7T TFET SRAM cell. We achieve a leakage reduction improvement of 700X and 1600X over traditional CMOS SRAM designs at V DD of 0.3V and 0.5V respectively which makes it suitable for use at ultra-low power applications.

In this paper, we experimentally demonstrate 100% enhancement in drive current (I ON) over In 0:53 Ga 0:47 As n-channel homojunction tunnel fieldeffect transistor (TFET) by replacing In 0:53 Ga 0:47 As source with a moderately staggered and lattice-matched GaAs 0:5 Sb 0:5. The enhancement is also compared with In 0:53 Ga 0:47 As N+ pocket ()-doped channel homojunction TFET. Utilizing calibrated numerical simulations, we extract the effective scaling length (eff) for the double gate, thin-body configuration of the staggered heterojunction and-doped channel TFETs. The extracted eff is shown to be lower than the geometrical scaling length, particularly in the highly staggered-source heterojunction TFET due to the reduced channel side component of the tunnel junction width, resulting in improved device scalability.

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With the continued miniaturization of MOSFETs, the OFF-state leakage current (I OFF) is exponentially increasing due to the nonscalability of the threshold voltage imposed by the fundamental 60 mV/decade subthreshold swing at room temperature. This limits the on current (I ON) and the I ON-I OFF ratio severely as the supply voltage is reduced. Interband tunnel transistor [1] features sub-60mV/dec subthreshold slope operation and can be used to circumvent this limitation. This paper examines the potential of double gate (DG) inter-band tunnel FETs (TFET) in 3 different material systems, Si, Ge and InAs, for logic circuit applications down to 0.25V supply voltage (V CC). Based on two-dimensional numerical drift-diffusion simulations [2], we show that 30nm gate length (L G) InAs (indium arsenide) based TFETs can achieve I ON /I OFF of >4x10 4 with <1 ps intrinsic delay at 0.25V V CC. The key features of the InAs TFETs are: a) asymmetric source drain design to suppress the ambipolar leakage b) use of a lower dielectric constant gate oxide (non high-K) and c) high source side injection velocity at moderate electric fields. The n-channel DG TFETs and MOSFETs used in this study have an L G of 30 nm and 2.5 nm thick SiO 2 or HfO 2 gate dielectrics. The typical body thickness (T body) is kept at 7 nm. Gaussian doping profiles with doping gradients of 2nm/decade are used for the source and drain regions. Despite the steep subthreshold slope and the I ON-I OFF ratio spanning 12 decades over 1V V GS swing, Si DG TFET I ON (105µA/µm) is much less than Si DG MOSFET I ON (2.27mA/µm) due to the poor tunneling rate of source side valence electrons into the channel conduction band (Fig. 2). Narrow gap semiconductors can enhance the source side tunneling rate due to the combined effects of both reduced barrier height and shorter tunneling distance in addition to the reduced tunneling mass. Figure 4-5 compare the I D-V GS characteristics of the Ge and InAs based DG TFETs with their MOSFET counterparts. Both Ge and InAs DG MOSFETs suffer from increased band to band tunneling at the drain end, which forward biases the source to channel junction and significantly degrades the I ON-I OFF ratio [3]. It's clearly seen that the performance difference between the TFET and the MOSFET is reduced with reducing bandgap and supply voltage of operation. In order to suppress the ambipolar characteristics, we use asymmetric source and drain doping in InAs DG TFETs which exhibits I ON-I OFF ratio of >4x10 4 at 0.25 V V CC. To further highlight the differences in carrier transport between conventional MOSFETs and tunnel FETs, we compared the field and velocity profiles in the channel. Due to the higher longitudinal field at the source side, the TFETs have higher source-side injection velocities compared to the MOSFETs. However, the carrier velocities slow down significantly in the TFETs while traversing the channel due to low electric field. Compositional bandgap grading could be harnessed to induce a quasi-electric field to accelerate carriers in th...