Experimental demonstration of 100nm channel length In&lt;inf&gt;0.53&lt;/inf&gt;Ga&lt;inf&gt;0.47&lt;/inf&gt;As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications

Mookerjea, S.; Mohata, Dheeraj; Krishnan, R.; Singh, Jawar; Vallett, Aaron; Ali, A.; Mayer, Theresa S.; Narayanan, V.; Schlom, Darrell G.; Liu, A.; Datta, Suman

doi:10.1109/iedm.2009.5424355

Cited by 100 publications

(70 citation statements)

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“…Recently, Inter-bank Tunneling Field Effect Transistors (TFETs) have shown to be the attractive candidates to operate at low supply voltages (e.g. 0.3V) with ultra low leakage and higher frequency than CMOS [9,10]. However, at higher supply voltage, CMOS devices are able to achieve much better performance than TFETs.…”

Section: Introductionmentioning

confidence: 99%

“…Traditional CMOS devices are limited to 60mV/decade sub-threshold slope which induces high leakage current during the voltage scaling [12]. While TFETs [9] exhibit sub-60mV/decade sub-threshold slope and achieve very low leakage power consumption at low supply voltage. Figure 2(a) compares the OFF-state leakage current (I OFF ) and ON current (I ON ) of the two kinds of devices when VCC is 0.3V.…”

Section: 2tunneling Field Effect Transistors (Tfets)mentioning

confidence: 99%

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Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Tan

2013

International Symposium on Quality Electronic Design (ISQED)

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State-of-the-art General-Purpose computing on Graphics Processing Unit (GPGPU) is facing severe power challenge due to the increasing number of cores placed on a chip with decreasing feature size. In order to hide the long latency operations, GPGPU employs the fine-grained multithreading among numerous active threads, leading to the sizeable register files with massive power consumption. Exploring the optimal power savings in register files becomes the critical and first step towards the energyefficient GPGPUs. The conventional method to reduce dynamic power consumption is the supply voltage scaling, and the inter-bank tunneling FETs (TFETs) are the promising candidates compared to CMOS for low voltage operations regarding to both leakage and performance. However, always executing at the low voltage (so that low frequency) will result in significant performance degradation. In this study, we propose the hybrid CMOS-TFET based register files. To optimize the register power consumption, we allocate TFET-based registers to threads whose execution progress can be delayed to some degree to avoid the memory contentions with other threads, and the CMOS-based registers are still used for threads requiring normal execution speed. Our experimental results show that the proposed technique achieves 30% energy (including both dynamic and leakage) reduction in register files with little performance degradation compared to the baseline case equipped with naive power optimization technique.

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Section: Introductionmentioning

confidence: 99%

Section: 2tunneling Field Effect Transistors (Tfets)mentioning

confidence: 99%

Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Tan

2013

International Symposium on Quality Electronic Design (ISQED)

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“…[4][5][6][7][8][9][10] III-V materials, such as InGaAs and GaSb, and their heterostructures have been used to fabricate nTFETs, which demonstrated high I ON due to the direct BTBT and high electron mobility. [11][12][13][14][15][16][17] While theoretical study showed that I ON of III-V pTFET is low due to the fundamental limitation of low density of conduction band states. Current pTFETs mainly employed group IV materials, such as SiGe, Ge, and GeSn.…”

Section: Introductionmentioning

confidence: 99%

Relaxed germanium-tin P-channel tunneling field-effect transistors fabricated on Si: impacts of Sn composition and uniaxial tensile strain

Han¹,

Wang²,

Liu³

et al. 2015

AIP Advances

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In this work, relaxed GeSn p-channel tunneling field-effect transistors (pTFETs) with various Sn compositions are fabricated on Si. Enhancement of on-state current ION with the increase of Sn composition is observed in transistors, due to the reduction of direct bandgap EG. Ge0.93Sn0.07 and Ge0.95Sn0.05 pTFETs achieve 110% and 75% enhancement in ION, respectively, compared to Ge0.97Sn0.03 devices, at VGS - VTH = VDS = - 1.0 V. For the first time, ION enhancement in GeSn pTFET utilizing uniaxial tensile strain is reported. By applying 0.14% uniaxial tensile strain along [110] channel direction, Ge0.95Sn0.05 pTFETs achieve 12% ION improvement, over unstrained control devices at VGS - VTH = VDS = - 1.0 V. Theoretical study demonstrates that uniaxial tensile strain leads to the reduction of direct EG and affects the reduced tunneling mass, which bring the GBTBT rising, benefiting the tunneling current enhancement in GeSn TFETs.

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“…Thus, a tunneling FET (TFET) has been considered as one of the most promising low-power devices [3]. The earlier TFET studies focused on on-current boosting by introducing various materials and device structures [4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Linearity of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

Choi

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Linearity characteristics of hetero-gatedielectric tunneling field-effect transistors (HG TFETs) have been compared with those of high-k-only and SiO 2 -only TFETs in terms of IIP3 and P1dB. It has been observed that the optimized HG TFETs have higher IIP3 and P1dB than high-k-only and SiO 2 -only TFETs. It is because HG TFETs show higher transconductance (g m ) and current drivability than SiO 2 -only TFETs and g m less sensitive to gate voltage than high-k-only TFETs.

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Experimental demonstration of 100nm channel length In<inf>0.53</inf>Ga<inf>0.47</inf>As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications

Cited by 100 publications

References 0 publications

Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Relaxed germanium-tin P-channel tunneling field-effect transistors fabricated on Si: impacts of Sn composition and uniaxial tensile strain

Linearity of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

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