A single ended 6T SRAM cell design for ultra-low-voltage applications

Singh, Jawar; Pradhan, Dhiraj K.; Hollis, Simon; Mohanty, Saraju P.

doi:10.1587/elex.5.750

Cited by 43 publications

(20 citation statements)

References 7 publications

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“…Upon the rise of WL, the BL line discharges through M6-M3 and the intermediate node Q is pulled up toward the precharged value of BL. This voltage rise of Q must stay low enough, which in the worst case could flip the cell [13,14]. Fig.…”

Section: Memory Cell Fluctuation Under Voltage Controlmentioning

confidence: 99%

A Novel Structure to Realize Memory Cell Fluctuation Under Voltage Control in Ising Chip

Wang¹,

Chen²,

Zhang³

2017

Proceedings of the International Conference on Computer Networks and Communication Technology (CNCT 2016)

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Abstract. New computing architecture utilizing the noise of integrated circuit to realize indeterminate computing has been proposed previously to solve combinatorial optimization problems. But the solution accuracy of realizing indeterminate computing with circuit's noise performed significantly worse than that with external random number. Because large scale of time is spent to introduce randomness in reading memory cells by row, which reduces the effective computing time. This paper presents a novel structure to introduce probabilistic behavior with just one read operation. It improves the rate of effective computing time and can get close solution accuracy to the scheme using external random number but with less cost.

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Section: Memory Cell Fluctuation Under Voltage Controlmentioning

confidence: 99%

A Novel Structure to Realize Memory Cell Fluctuation Under Voltage Control in Ising Chip

Wang¹,

Chen²,

Zhang³

2017

Proceedings of the International Conference on Computer Networks and Communication Technology (CNCT 2016)

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“…Sizing for read and write could be done independently. SRAM cell by Singh et al uses SE decoupled read and write assist technique for SE write [4]. A low power technique by using separate read and write circuits is proposed in [5].…”

Section: Existing Implementationsmentioning

confidence: 99%

Charge sharing based 10T SRAM for low-power

Maroof

Sohail

Shin

2016

IEICE Electron. Express

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We propose a novel charge sharing bit-line 10T SRAM for differential read and single ended (SE) write. Decoupled read provides high noise margin. Read bit-lines are not charged to full V DD , and these share charge for read 1 operation. A new write driver is proposed for SE write which charges the write-bit-line conditionally. Virtual power rail is used to suppress bit-line leakages. Compared with 6T SRAM, charge sharing scheme potentially consumes only 25% read and 50% write dynamic power. Thorough comparisons with 6T at 45 nm node show that the proposed 10T design has 2× read static noise margin, 71% reduction in total read and 48% reduction in total write power.

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“…Due to this problem, 6T SRAM cell and its variants cannot be operated at reduced supply voltages without parametric and functional failure causing yield loss. Single-ended 6T SRAM cell [11] suffers from write delay. Write assist circuits are required for proper operation of 6T cell.…”

Section: Standard 6t Sram Cellmentioning

confidence: 99%