Charge sharing based 10T SRAM for low-power

Maroof, Naeem; Sohail, Muhammad; Shin, Hyunchul

doi:10.1587/elex.13.20151033

Cited by 3 publications

(2 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The conventional 6T SRAM is widely used because of its simple structure and small area. However, the conventional 6T bitcell has conflicts in writability and read stability in transistor size design, which leads to read and write errors under sub-threshold voltage [10,11,12]. The minimum operating voltage of 6T SRAM is limited to around 700 mV [13].…”

Section: Introductionmentioning

confidence: 99%

A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM

Shi

Jia

Yin

et al. 2022

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a half-selected robust 12T bitcell with builtin write-assist for sub-threshold SRAM. The proposed 12T bitcell is robust enough in bit-interleaving architecture to enhance soft-error immunity combined with error correction code. The read stability of the proposed bitcell is improved by read decoupled. The writability is improved by data-dependent supply-cutoff write-assist. Both row and column f-selected bitcells can hold data stably during write operations. Simulation results based on a standard 55 nm CMOS technology show that the read static noise margin of the proposed bitcell is 16.13x as that of the conventional 6T bitcell. Moreover, the write failure in the sub-threshold region is eliminated. In addition, the leakage consumption is improved by 15.7% compared with 6T bitcell.

show abstract

Section: Introductionmentioning

confidence: 99%

A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM

Shi

Jia

Yin

et al. 2022

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…In this paper, we present details of our decoupled differential read (DDR) port , its associated BL pre‐charging scheme, and the SA architecture for low‐power SRAM. Decoupled read operation provides higher read stability and allows subthreshold operation.…”

Section: Introductionmentioning

confidence: 99%

Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs

Maroof

Sohail

Shin

2016

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

In this paper, we present our decoupled differential read (DDR) port and bitline (BL) pre-charging scheme. The proposed scheme allows the charge sharing between bitlines during the read operation. DDR port isolates the internal nodes, thus improves the read static noise margin and allows the subthreshold operation. BLs are not pre-charged to full V DD . Read port is designed such that for the read '1' operation, BL shares its charge with BLB, and for read '0' operation, BL is charged toward V DD and BLB is discharged to the ground. The proposed non-V DD BL pre-charging and the charge-sharing mechanism provide substantial read power savings. Virtual power rail is used to suppress the BL leakages. A dynamic voltage level shifting preamplifier is used that shifts both BLs to the middle voltage and amplifies the voltage difference. Single-ended write driver is also presented that only conditionally charges the write BL. The proposed 10-transistor static random access memory cell using DDR provides more than 2 times read static noise margin,~72% read power savings, and~40% write power savings compared with the conventional six-transistor static random access memory. sense amplifier (SA), and write driver are shared by a column. A 6T bit cell and SA are also shown in the figure.Voltage scaling is the most effective knob for reducing power consumption. Low-voltage operation of SRAM is of keen interests to the research community. Several different SRAM cells, array architectures, and assist techniques have been proposed as the conventional 6T SRAM designs fail to operate at low voltages. A conventional eight-transistor (8T) SRAM employs two (02) more transistors per cell to decouple the internal nodes from read current path and achieves a high read static noise margin (RSNM). However, 8T offers single-ended (SE) operation, which makes sensing operation very challenging. SRAM cells like nine transistors (9T) [3] and seven transistors [4] cut off the storage nodes from read path by using isolation transistors. However, both of these use SE read operation like conventional 8T cell. Another 8T cell by Saieidi et al. [5] employs the same technique and provides the differential read scheme. Nevertheless, internal node voltages of [5] floats during the read operation are affected due to the capacitive coupling. A 9T cell by Liu and Kursun [6] and another 9T cell by Ltkemeier et al. [7] have differential read decoupled capability. A 10-transistor (10T) SRAM cell by Calhoun et al. [8] reduces the cell leakages at the cost of read speed and provides SE read operation. Another 9T cell by Wang et al. [9] uses a SE read port and provides the equalized leakage for read '0' and read '1' case.These state-of-the-art designs provide certain benefits and lack in others. For example, SEdecoupled read provides higher read stability (RSNM); nevertheless, it makes sensing operation quite challenging and power hungry. SE SRAM would require twice as much ΔV BL as does the differential scheme. However, differential read-decoupled ports either req...

show abstract

Low leakage, differential read scheme CNTFET based 9T SRAM cells for Low Power applications

Valluri

Musala

2022

International Journal of Electronics

View full text Add to dashboard Cite

Charge sharing based 10T SRAM for low-power

Cited by 3 publications

References 11 publications

A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM

A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM

Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs

Low leakage, differential read scheme CNTFET based 9T SRAM cells for Low Power applications

Contact Info

Product

Resources

About