Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs

Abstract

In this paper, we present our decoupled differential read (DDR) port and bitline (BL) pre-charging scheme. The proposed scheme allows the charge sharing between bitlines during the read operation. DDR port isolates the internal nodes, thus improves the read static noise margin and allows the subthreshold operation. BLs are not pre-charged to full V DD . Read port is designed such that for the read '1' operation, BL shares its charge with BLB, and for read '0' operation, BL is charged toward V DD and BLB is discharged to the ground. The proposed non-V DD BL pre-charging and the charge-sharing mechanism provide substantial read power savings. Virtual power rail is used to suppress the BL leakages. A dynamic voltage level shifting preamplifier is used that shifts both BLs to the middle voltage and amplifies the voltage difference. Single-ended write driver is also presented that only conditionally charges the write BL. The proposed 10-transistor static random access memory cell using DDR provides more than 2 times read static noise margin,~72% read power savings, and~40% write power savings compared with the conventional six-transistor static random access memory. sense amplifier (SA), and write driver are shared by a column. A 6T bit cell and SA are also shown in the figure.Voltage scaling is the most effective knob for reducing power consumption. Low-voltage operation of SRAM is of keen interests to the research community. Several different SRAM cells, array architectures, and assist techniques have been proposed as the conventional 6T SRAM designs fail to operate at low voltages. A conventional eight-transistor (8T) SRAM employs two (02) more transistors per cell to decouple the internal nodes from read current path and achieves a high read static noise margin (RSNM). However, 8T offers single-ended (SE) operation, which makes sensing operation very challenging. SRAM cells like nine transistors (9T) [3] and seven transistors [4] cut off the storage nodes from read path by using isolation transistors. However, both of these use SE read operation like conventional 8T cell. Another 8T cell by Saieidi et al. [5] employs the same technique and provides the differential read scheme. Nevertheless, internal node voltages of [5] floats during the read operation are affected due to the capacitive coupling. A 9T cell by Liu and Kursun [6] and another 9T cell by Ltkemeier et al. [7] have differential read decoupled capability. A 10-transistor (10T) SRAM cell by Calhoun et al. [8] reduces the cell leakages at the cost of read speed and provides SE read operation. Another 9T cell by Wang et al. [9] uses a SE read port and provides the equalized leakage for read '0' and read '1' case.These state-of-the-art designs provide certain benefits and lack in others. For example, SEdecoupled read provides higher read stability (RSNM); nevertheless, it makes sensing operation quite challenging and power hungry. SE SRAM would require twice as much ΔV BL as does the differential scheme. However, differential read-decoupled ports either req...

A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes

“…A provision to reduce the leakage power was also incorporated whereby the stacking devices in each of the inverter. In Maroof et al, 16 a 10T cell using the charge sharing mechanism between the bit lines has been proposed, which avoids the need of bit line to be precharged up to complete V DD voltage. Hence, the cells become prone towards the leakage current and noise occurrence.…”

“…But it demands for an additional boosted supply and also involved extra processing steps during fabrication. In Maroof et al, 16 a 10T cell using the charge sharing mechanism between the bit lines has been proposed, which avoids the need of bit line to be precharged up to complete V DD voltage. It results in the improved low-power memory cell, but there is no specific strategy incorporated to improve the write stability.…”

Charge sharing write driver and half‐ pre‐charge 8T SRAM with virtual ground for low‐power write and read operation

“…Many designs and techniques have been introduced to: lower the [7–10], the [11–14], improve the of the RBL [15–19] which allows more cells to be integrated on a single BL column, and others [20–22] provide alternative cells and techniques for robust read operation. Less of the work has been done on WDs and conventional SRAM WD has few variants [3].…”