The dynamic processing of optoelectronic signals carrying temporal and sequential information is critical to various machine learning applications including language processing and computer vision. Despite extensive efforts to emulate the visual cortex of human brain, large energy/time overhead and extra hardware costs are incurred by the physically separated sensing, memory, and processing units. The challenge is further intensified by the tedious training of conventional recurrent neural networks for edge deployment. Here, we report in-sensor reservoir computing for language learning. High dimensionality, nonlinearity, and fading memory for the in-sensor reservoir were achieved via two-dimensional memristors based on tin sulfide (SnS), uniquely having dual-type defect states associated with Sn and S vacancies. Our in-sensor reservoir computing demonstrates an accuracy of 91% to classify short sentences of language, thus shedding light on a low training cost and the real-time solution for processing temporal and sequential signals for machine learning applications at the edge.

The large-scale crossbar array is a promising architecture for hardware-amenable energy efficient three-dimensional memory and neuromorphic computing systems. While accessing a memory cell with negligible sneak currents remains a fundamental issue in the crossbar array architecture, up-to-date memory cells for large-scale crossbar arrays suffer from process and device integration (one selector one resistor) or destructive read operation (complementary resistive switching). Here, we introduce a self-selective memory cell based on hexagonal boron nitride and graphene in a vertical heterostructure. Combining non-volatile and volatile memory operations in the two hexagonal boron nitride layers, we demonstrate a self-selectivity of 10 10 with an on/off resistance ratio larger than 10 3 . The graphene layer efficiently blocks the diffusion of volatile silver filaments to integrate the volatile and non-volatile kinetics in a novel way. Our self-selective memory minimizes sneak currents on large-scale memory operation, thereby achieving a practical readout margin for terabit-scale and energy-efficient memory integration.

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A high-slew-rate, low-power, CMOS, rail-to-rail buffer amplifier for large flat-panel-display (FPD) applications is proposed. The major circuit of the output buffer is a rail-to-rail, folded-cascode, class-AB amplifier which can control the tail current source using a compact, novel, adaptive biasing scheme. The proposed output buffer amplifier enhances the slew rate throughout the entire rail-to-rail input signal range. To obtain a high slew rate and low power consumption without increasing the static current, the tail current source of the adaptive biasing generates extra current during the transition time of the output buffer amplifier. A column driver IC incorporating the proposed buffer amplifier was fabricated in a 1.6-μm 18-V CMOS technology, whose evaluation results indicated that the static current was reduced by up to 39.2% when providing an identical settling time. The proposed amplifier also achieved up to 49.1% (90% falling) and 19.9 % (99.9% falling) improvements in terms of settling time for almost the same static current drawn and active area occupied.

A novel high-speed column-line driving scheme having output buffer amplifiers embedded with polarity multiplexer switches is proposed for use in large-sized thin-film transistor liquid-crystal displays. The proposed driving scheme does not have explicit output-polarity switches, resulting in lower settling time. Experimental results in a 1.2 μm 13.5 V CMOS process indicated that using the proposed driving scheme the settling times to reach 99% of target voltages for the dot and column inversions were improved by up to 48.6%. This driving scheme can be applied to class AB-or class B-type amplifiers for liquid-crystal display column drivers and output buffers controlled by output switches.