Charge-Plasma Based Process Variation Immune Junctionless Transistor

Abstract

In this letter, we report for the first time a distinctive approach of implementing a junctionless transistor (JLT) without doping (doping-less) the ultrathin silicon film. A charge-plasma concept is employed to induce n-region for the formation of source and drain for a n-channel JLT using appropriate metal work function electrodes. Electrical characteristics of the proposed device are simulated and compared with that of a conventionally doped JLT of identical dimensions. In conventional JLTs, the channel doping concentration is generally kept high to ensure high ON-state current, but it causes variation in threshold voltage, which may be due to process variations. The proposed device solves the problem of threshold voltage variability without affecting inherent advantages of JLTs.

Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

“…4,5 Furthermore, JLFET demonstrating high temperature robustness have been reported. [6][7][8] We have combined the advantages of the SBFET and JLFET concepts on SOI in a novel asymmetric dual gate but single channel device. This combination improves the high temperature robustness as reported recently for our SiNW FETs.…”

“…8. Furthermore, as no conventional impurity doping process is required, the device does not suffer from dopant dependent reduction of carrier mobility or statistic dopant fluctuation and resulting threshold voltage variation following the argumentation of 6 for JLFET devices. In addition, the degree of freedom to instantly select n-and ptype behavior via an ordinary electrical signal of appropriate polarity on the BG allows designing reconfigurable circuits with increased functionality.…”

Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET

“…Another concern of doping devices is thermal budget because of the ion implantation and expensive annealing techniques. So, this proposed doping less device can successfully eliminate the above said problems [19,20].…”

“…The concept of doping less is adopted from Kumar and Nadda [18]. For fulfillment of the requirements for doping less concept, the work function of source/drain and silicon body thickness (t Si ) is considered as 3.9 eV and 10 nm respectively [19,20]. According to ITRS the drain bias has been fixed at V DD = 0.7 V [21].…”

Investigation of laterally single-diffused metal oxide semiconductor (LSMOS) field effect transistor

“…The "n + " source/drain regions and "p + " body contact are formed using the charge plasma concept by using metal electrodes of a specific work function [10,11]. The charge plasma concept is used to realize both low power devices [12][13][14][15][16][17][18][19][20][21][22][23][24][25] and a high power p-i-n diode [26]. We show in this work that LDMOS can also be implemented using the charge plasma principle and consequently reduce the number of thermal steps required during the fabrication.…”