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In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establish Schottky barrier FET (SBFET) operation and one front-gate forming a junctionless FET (JLFET) for actual current control, significantly increases the temperature robustness of the device. The dominating leakage path for OFF-state currents in today's downscaled MOSFET devices originate from PN-junction and bulk leakage.1,2 These leakage currents increase severely with temperature. SOI technologies can significantly reduce bulk leakage currents. However, junction leakage because of reversed bias PN-junctions is still present in SOI MOSFETs.2 Therefore, our device concept replaces conventional S/D PN-junctions with Schottky barrier contacts in a virtually dopant-free CMOS environment. Many groups have demonstrated the advantages of SBFET devices like low S/D resistance as well as abrupt junctions enabling further scaling and suppression of parasitic bipolar behavior.4,5 Furthermore, JLFET demonstrating high temperature robustness have been reported. [6][7][8] We have combined the advantages of the SBFET and JLFET concepts on SOI in a novel asymmetric dual gate but single channel device. This combination improves the high temperature robustness as reported recently for our SiNW FETs.9,10 For the first time, we have successfully extended this 3D-SiNW concept to planar, non-nanowire device structures.We found that the combination of an ambipolar electrostatic doping back-gate (BG) in addition to an electrically separated current flow control front-gate (FG) in a single device results in a superior on-tooff current ratio and leakage suppression at high temperatures. The BG transistor as a SBFET shows an ambipolar behavior similar to the SBFET reported in.11 On the other hand, the unipolar FG transistor resembles the behavior of a JLFET as reported in Ref. 8. Furthermore, as no conventional impurity doping process is required, the device does not suffer from dopant dependent reduction of carrier mobility or statistic dopant fluctuation and resulting threshold voltage variation following the argumentation of 6 for JLFET devices. In addition, the degree of freedom to instantly select n-and ptype behavior via an ordinary electrical signal of appropriate polarity on the BG allows designing reconfigurable circuits with increased functionality.12 Until now, all ambipolar devices using a separate gate to control the current flow between source and drain involve nanowire structures as, for example, silicon nanowires or carbon nanotubes....

Abstract-In this paper, we demonstrate by simulation the feasibility of electrostatically doped and therefore reconfigurable planar field-effect-transistor (FET) structure which is based on our already fabricated and published Si-nanowire (SiNW) devices. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a siliconon-insulator (SOI) substrate. The transistor type, i.e. n-type or ptype FET, is electrically selectable on the fly by applying an appropriate control-gate voltage which significantly increases the versatility and flexibility in the design of digital integrated circuits.

In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The fabricated MG-NWFETs are originally ambipolar nanowire devices with midgap Schottky-barriers serving as S/D contacts. A tri-gate structure is used as front-gate for current control across the NWFET whereas a planar back-gate is used to select the desired unipolar device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively. Both, logic and memory devices can be realized with the same simple nanowire structure.

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