Patterned growth of freestanding carbon nanotube͑s͒ on submicron nickel dot͑s͒ on silicon has been achieved by plasma-enhanced-hot-filament-chemical-vapor deposition ͑PE-HF-CVD͒. A thin film nickel grid was fabricated on a silicon wafer by standard microlithographic techniques, and the PE-HF-CVD was done using acetylene (C 2 H 2 ) gas as the carbon source and ammonia (NH 3 ) as a catalyst and dilution gas. Well separated, single carbon nanotubes were observed to grow on the grid. The structures had rounded base diameters of approximately 150 nm, heights ranging from 0.1 to 5 m, and sharp pointed tips. Transmission electron microscopy cross-sectional image clearly showed that the structures are indeed hollow nanotubes. The diameter and height depend on the nickel dot size and growth time, respectively. This nanotube growth process is compatible with silicon integrated circuit processing. Using this method, devices requiring freestanding vertical carbon nanotube͑s͒ such as scanning probe microscopy, field emission flat panel displays, etc. can be fabricated without difficulty.

The Stark splitting of a single fourfold degenerate impurity located within the built-in potential of a metal-semiconductor contact is investigated using low temperature transport measurements. A model is developed and used to analyze transport as a function of temperature, bias voltage, and magnetic field. Our data is consistent with a boron impurity. We report g factors of g_{1/2}=1.14 and g_{3/2}=1.72 and a linear Stark splitting 2Delta of 0.1 meV.

Microstructures of well-aligned multiwall carbon nanotubes grown on patterned nickel nanodots and uniform thin films by plasma-enhanced chemical vapor deposition have been studied by electron microscopy. It was found that growth of carbon nanotubes on patterned nickel nanodots and uniform thin films is different. During growth of carbon nanotubes, a nickel particle sits at the tip of each nanotube, and its [220] is preferentially oriented along the plasma direction, which can be explained by a channeling effect of ions coming into nickel particles in plasma. The alignment of nanotubes is induced by the electrical field direction relative to substrate surface.

International audienceBayesian inference is a powerful approach for integrating independent conflicting information for decision-making. Though an important component of robotic, biological, and other sensory-motors systems, general-purpose computers perform Bayesian inference with limited efficiency. Here we show that Bayesian inference can be efficiently performed with stochastic signals, which are particularly adapted to novel low power nano-devices that exhibit faults and device variations. A simple Muller C-element directly implements Bayes' rule. Complex inferences are performed by C-element trees, which compute the probability of an event based on multiple independent sources of evidence. A naïve Bayesian spam filter circuit is demonstrated as a pedagogical application, and design techniques for improving circuit functionality are described. Limitations of this structure are discussed in terms of signal autocorrelation. The stochastic inference structure is exceptionally robust to faults, an essential feature of decision circuits, and can therefore leverage the increased efficiency of emerging nanodevices. This hardware implementation of Bayesian inference is extremely area and power efficient, with an area-energy-delay product several orders of magnitude less than the conventional floating point implementation. These results open a pathway for a direct stochastic hardware implementation of Bayesian inference, enabling a new class of embedded decision circuits for robotics and medical applications

We report nonmonotonicities in the low-temperature current versus gate voltage characteristics of PtSi/Si Schottky Barrier metal–oxide–semiconductor field-effect transistors. Direct tunneling through the Schottky barrier is shown to limit the current and be superimposed with resonant peaks and oscillations. These structures are attributed to resonant tunneling through impurities located close to the interface and nonuniformities of the heterojunction. We thus demonstrate barrier height variations in electron transport through a relatively large metal/semiconductor contact area. The inhomogeneities result in different average Schottky barrier heights between devices, and cause height variations as a function of carrier concentration within a metal/semiconductor interface.

We report the fabrication of multi-island single-electron devices made by lithographic contacting of selfassembled alkanethiol-coated gold nanocrystals. The advantages of this method, which bridges the dimensional gap between lithographic and NC sizes, are (1) that all tunnel junctions are defined by self-assembly rather than lithography and (2) that the ratio of gate capacitance to total capacitance is high. The rich electronic behavior of a double-island device, measured at 4.2 K, is predicted in detail by combining finite element and Monte Carlo simulations with the standard theory of Coulomb blockade with very few adjustable parameters.

We explore the low temperature transport through a resonant acceptor impurity located near a metalsemiconductor interface and observe a large shift ͑12 meV͒ and splitting ͑0.8 meV͒ of its ground state. The shift is attributed to the quadratic Stark effect resulting from the electric field of the electrostatic barrier. The splitting is too large to be attributed to a linear Stark splitting. We calculate the strain field due to a nearby point defect and show that it can cause a large ground state splitting.

In this article we investigate the subthreshold behavior of PtSi source/drain Schottky barrier metal–oxide–semiconductor field-effect transistors. We demonstrate very large on/off ratios on bulk silicon devices and show that slight process variations can result in anomalous leakage paths that degrade the subthreshold swing and complicate investigations of device scaling.