By means of catalytic chemical vapor deposition (CCVD) in-situ grown monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate without the need to transfer graphene layers. In-situ grown MoLGFETs exhibit the expected Dirac point together with the typical low on/off-current ratios. In contrast, BiLGFETs possess unipolar p-type device characteristics with an extremely high on/off-current ratio up to 1×10 7. The complete fabrication process is silicon CMOS compatible. This will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment

We invented a method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. To stimulate the growth of graphene layers on oxidized silicon a catalyst system of nanometer thin aluminum/nickel double layer is used. This catalyst system is structured via liftoff before the wafer enters the catalytic chemical vapor deposition (CCVD) chamber. In the subsequent methane based growth process monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate, whereby the number of stacked graphene layers is determined by the selected CCVD process parameters, e.g. temperature and gas mixture. Subsequently, Raman spectroscopy is performed within the channel region in between the catalytic areas and the Raman spectra of fivelayer, bilayer and monolayer graphene confirm the existence of graphene grown by this silicon-compatible, transfer-free and in-situ fabrication approach. These graphene FETs will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment.2

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In this work, fully functional carbon nanotube field-effect transistors (CNT-FETs) have been fabricated using a simple and inexpensive process including in-situ chemical vapor deposition (CVD) growth of the nanotubes. The temperature used is 900 C and the catalyst layer is nickel on aluminum. Simultaneously, the catalyst metal areas are used as source/drain electrodes. The CNT-FET fabrication is compatible with conventional complementary metal oxide semiconductor (CMOS) technology. For process optimization, every major process step is controlled by atomic force microscopy (AFM). The nondestructive AFM technique provides both a complete overview of the structures as well as the detailed geometrical properties of the nanotubes. We have also fabricated CNT-FET test structures in which the source/drain electrodes have a direct conductive path to the substrate, in order to perform electrical measurements at the nanoscale by conductive AFM (C-AFM). In this way, we obtain current images of the structures and the electrical characteristics of each individual nanotube can be measured.

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