Reconfigurable CMOS with undoped silicon nanowire midgap Schottky-barrier FETs

Wessely, Frank; Krauss, Tillmann; Schwalke, Udo

doi:10.1016/j.mejo.2012.08.004

Cited by 27 publications

(13 citation statements)

References 9 publications

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“…1. It is partly based on our published SiNW FET technology [3], [4], [5]. The new concept, as well as the previous the SiNW technology, is experimentally based on a virtually undoped SOI substrate, i.e.…”

Section: Device Structurementioning

confidence: 99%

“…The Schottky barrier parameters for the simulation of the S/D contacts have been estimated by comparing and fitting simulated and measured back-gate voltage sweeps of the fabricated SiNW FET devices with 70 nm x 70 nm rectangular diameter and 50um length ( Fig. 5) [3], [4], [5]. Remaining deviations between measurement and simulation are mainly caused by differences in device and contact geometries as well as not modeled complex Schottky barrier effects (not shown here) as, for example, barrier lowering due to image charges.…”

Section: A Back-gate Enhancement Mode Operationmentioning

confidence: 99%

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Electrically reconfigurable dual metal-gate planar field-effect transistor for dopant-free CMOS

Krauss

Wessely

Schwalke

2016

2016 13th International Multi-Conference on Systems, Signals &Amp; Devices (SSD)

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Abstract-In this paper, we demonstrate by simulation the feasibility of electrostatically doped and therefore reconfigurable planar field-effect-transistor (FET) structure which is based on our already fabricated and published Si-nanowire (SiNW) devices. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a siliconon-insulator (SOI) substrate. The transistor type, i.e. n-type or ptype FET, is electrically selectable on the fly by applying an appropriate control-gate voltage which significantly increases the versatility and flexibility in the design of digital integrated circuits.

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Section: Device Structurementioning

confidence: 99%

Section: A Back-gate Enhancement Mode Operationmentioning

confidence: 99%

Electrically reconfigurable dual metal-gate planar field-effect transistor for dopant-free CMOS

Krauss

Wessely

Schwalke

2016

2016 13th International Multi-Conference on Systems, Signals &Amp; Devices (SSD)

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“…Related results regarding non-midgap SB contacts are discussed in-depth in our previous work on Si-NW transistors in Ref. 9. By using Schottky barrier height engineering it is thought to be possible to compensate the temperature dependent decrease of carrier mobility by the increase of thermionic (field-) emission in order to realize an intrinsically temperature compensated transistor.…”

Section: Bg / Fg Biasingmentioning

confidence: 99%

“…This combination improves the high temperature robustness as reported recently for our SiNW FETs. 9,10 For the first time, we have successfully extended this 3D-SiNW concept to planar, non-nanowire device structures.…”

mentioning

confidence: 99%

Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

Krauss

Wessely

Schwalke

2015

ECS J. Solid State Sci. Technol.

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In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establish Schottky barrier FET (SBFET) operation and one front-gate forming a junctionless FET (JLFET) for actual current control, significantly increases the temperature robustness of the device. The dominating leakage path for OFF-state currents in today's downscaled MOSFET devices originate from PN-junction and bulk leakage.1,2 These leakage currents increase severely with temperature. SOI technologies can significantly reduce bulk leakage currents. However, junction leakage because of reversed bias PN-junctions is still present in SOI MOSFETs.2 Therefore, our device concept replaces conventional S/D PN-junctions with Schottky barrier contacts in a virtually dopant-free CMOS environment. Many groups have demonstrated the advantages of SBFET devices like low S/D resistance as well as abrupt junctions enabling further scaling and suppression of parasitic bipolar behavior.4,5 Furthermore, JLFET demonstrating high temperature robustness have been reported. [6][7][8] We have combined the advantages of the SBFET and JLFET concepts on SOI in a novel asymmetric dual gate but single channel device. This combination improves the high temperature robustness as reported recently for our SiNW FETs.9,10 For the first time, we have successfully extended this 3D-SiNW concept to planar, non-nanowire device structures.We found that the combination of an ambipolar electrostatic doping back-gate (BG) in addition to an electrically separated current flow control front-gate (FG) in a single device results in a superior on-tooff current ratio and leakage suppression at high temperatures. The BG transistor as a SBFET shows an ambipolar behavior similar to the SBFET reported in.11 On the other hand, the unipolar FG transistor resembles the behavior of a JLFET as reported in Ref. 8. Furthermore, as no conventional impurity doping process is required, the device does not suffer from dopant dependent reduction of carrier mobility or statistic dopant fluctuation and resulting threshold voltage variation following the argumentation of 6 for JLFET devices. In addition, the degree of freedom to instantly select n-and ptype behavior via an ordinary electrical signal of appropriate polarity on the BG allows designing reconfigurable circuits with increased functionality.12 Until now, all ambipolar devices using a separate gate to control the current flow between source and drain involve nanowire structures as, for example, silicon nanowires or carbon nanotubes....

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“…O óxido de formar um contato tipo Schottky com o silício. A utilização do siliceto de níquel, cuja função trabalho vale entre 4,7eV e 4,8eV, cria barreiras de potencial de tamanhos simétricos tanto para lacunas quanto para elétrons[22]. Isto possibilita a formação da camada de lacunas caso VGB<0 ou a formação da camada de elétrons caso VGB>0 na segunda interface, o que não ocorria na primeira versão do BE SOI MOSFET pois os contatos de alumínio propiciavam barreiras de potencial para elétrons maior do que para lacunas.…”

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Estudo, caracterização elétrica e modelagem de transistores BE (Back Enhanced) SOI MOSFET.

Yojo¹

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Reconfigurable CMOS with undoped silicon nanowire midgap Schottky-barrier FETs

Cited by 27 publications

References 9 publications

Electrically reconfigurable dual metal-gate planar field-effect transistor for dopant-free CMOS

Electrically reconfigurable dual metal-gate planar field-effect transistor for dopant-free CMOS

Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

Estudo, caracterização elétrica e modelagem de transistores BE (Back Enhanced) SOI MOSFET.

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