In this letter, we report for the first time a distinctive approach of implementing a junctionless transistor (JLT) without doping (doping-less) the ultrathin silicon film. A charge-plasma concept is employed to induce n-region for the formation of source and drain for a n-channel JLT using appropriate metal work function electrodes. Electrical characteristics of the proposed device are simulated and compared with that of a conventionally doped JLT of identical dimensions. In conventional JLTs, the channel doping concentration is generally kept high to ensure high ON-state current, but it causes variation in threshold voltage, which may be due to process variations. The proposed device solves the problem of threshold voltage variability without affecting inherent advantages of JLTs.

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In this paper, we report the potential benefits of dopingless double-gate field-effect transistor (DL-DGFET) designed on ultrathin silicon on insulator film for low power applications. The simulation results show that the proposed device exhibits higher ON current and less sensitivity toward device parameter variation compared with highly doped junctionless (JL) DGFET. The constraints of high metal gate workfunction of JL device are also relaxed using midgap materials as a gate electrode in the DL-DGFETs. Sensitivity analysis shows that the DL-DGFET exhibits least sensitivity to device parameter variation especially gate length due to suppression of short-channel effects. The DL-DGFET also shows lower static power dissipation in OFF state and lower intrinsic delay in ON state. The mixed-mode simulation of 6T-static random access memory cell using DL-DGFET shows impressive read and hold noise margins of 147 and 352 mV at V DD = 0.8 V for ultralow power applications. The possible fabrication process flow of DL-DGFET is also proposed.

A novel symmetric structure of bipolar charge-plasma transistor (BCPT) is presented. It consists of symmetrical gates with platinum on top of a thin intrinsic silicon film, which forms hole plasma in emitter and collector regions. The base contact is formed with hafnium metal to induce electron plasma; hence, a p-n-p chargeplasma transistor is formed without any doping. The collector area that is chosen is the same as an emitter to make the device symmetrical. 2D simulation results revealed that the proposed BCPT possesses higher collector current and higher current gain than conventional p-n-p bipolar junction transistor (BJT) and almost the same characteristics such as asymmetrical p-n-p BCPT for different geometries. The major challenge of poor cut-off frequency ( f T ) of BCPT is also addressed by optimising the silicon film thickness and intrinsic gaps.Introduction: In silicon-on-insulator (SOI) BiCMOS technology, the bipolar transistor is a promising candidate for high-speed radiofrequency silicon-on-chip applications, but its complex fabrication process makes the technology expensive [1]. To overcome this problem, a distinct approach of implementing a p-n junction diode using a charge-plasma concept was proposed in [2,3], and showed a good rectifying behaviour of the p-n junction without any ion implantation. In [4], the same concept was employed for the bipolar chargeplasma transistor (BCPT), and recently we have also shown the feasibility of charge plasma for junctionless metal-oxide semiconductor field effect transistor (MOSFET) [5].In this Letter we propose, for the first time, a symmetric structure of BCPT on an undoped SOI, where the emitter and collector regions are exchangeable similar to source and drain in MOSFET. From Fig. 1a, one can see that the same metal platinum (workfunction = 5.65 eV) is employed to form both the emitter and collector regions of equal area. However, in [4], two different metals were employed to realise the electrodes of the emitter and collector terminals separately and the collector area is kept higher than emitter, as shown in Fig. 1b. The symmetric structure of the proposed device yields the following advantages: (a) the emitter and collector terminals are exchangeable, i.e. easy integration (b) reduced overall device area, i.e. higher density and (c) reduced process complexity during the metal deposition process due to employment of same metal electrode in both emitter and collector regions, i.e. reduced fabrication cost. Furthermore, the proposed device is free from statistical doping fluctuations and doping control issues, and it can be processed at low temperatures. The simulation results show that the symmetric BCPT device exhibits almost the same results as that of the asymmetric BCPT and a good transistor action with a large current gain when compared with conventional bipolar junction transistor (BJT). Optimisation of silicon film thickness (t si ) and intrinsic gaps (L s ) have also shown a tremendous improvement in f T .

The concept of an electrically doped dynamically configurable fieldeffect transistor (FET) is presented, which provides freedom to dynamically switch between a high-performance MOSFET and a low-power tunnel FET that can be ideal for complementary circuit implementation. The charge carrier concentration, polarity and conduction mechanism of the device are precisely controlled by the appropriate application of an external polarity control signal, instead of the conventional ion-implantation process. Two-dimensional TCAD simulation results confirm the dynamic configuration of the proposed device and good functionality agreement with existing devices as well as it having the requisite qualities for low-power and high-performance applications.Introduction: Tunnel field-effect transistors (TFETs) have major performance advantages over conventional MOSFETs due to the steepness of the transition slope from the off to the on state and very low off-state current. For moderate performance requirements, TFETs not only offer a better I on /I off ratio, but also power savings and superior performance for the same voltage over MOSFETs [1]. However, for higher performance requirements, MOSFETs are attractive options [2,3]. To achieve computationally efficient (simultaneous improvement in performance and power savings) FETs, both (TFETs and MOSFETs) transistors need to be integrated into circuits that can extend the Boolean functionality of the complementary metal-oxide-semiconductor (CMOS) technology. Further, lightly doped TFETs and MOSFETs offer less susceptibility to random variability in device performance due to reduced random dopant fluctuations (RDFs) and an absence of an abrupt doping profile at the S/D junctions; as a result, the proposed device may have significantly less sensitivity to process parameter variations, reduced fabrication complexity, the thermal budget and leakage current [4].In this Letter, we propose an electrically doped dynamically configurable double-gate FET that can be configured dynamically by applying an appropriate polarity bias. In other words, the same device can be operated either as a TFET or MOSFET, hence yielding the benefits of both devices and the freedom to dynamically switch between high-performance and low-power (power saving) applications. Apart from dynamically switching between the TFET and the MOSFET, the polarity (n-and p-type) of the proposed device can also be controlled dynamically. The concept of dynamic configurability is based on the electrically doped source and drain regions, instead of relying on the abrupt doping profile at the junctions. The proposed device employs the same concept for realisation of dynamically configurable TFETs and MOSFETs, and they can be programmed dynamically to an n-TFET (or MOSFET) or p-TFET (or MOSFET). Recently, configurable logic gates using polarity-controlled silicon nanowire (SiNW) FETs have been demonstrated with configurable n-and p-MOSFETs using extra polarity gates (PGs) and they have shown good potential for higher packaging density ...

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