PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET

Lahgere, Avinash; Sahu, Chitrakant; Singh, Jawar

doi:10.1109/ted.2015.2446615

Cited by 69 publications

(29 citation statements)

References 25 publications

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“…Furthermore, TFETs employing this technique do not require physical doping and hence, are known as doping less TFETs (DL TFETs) [13]. These devices have shown amazing benefits such as immunity towards RDFs and susceptibility towards parametric variations because of DL design [14]. Also, the DLTFET eliminates the requirement of high-temperature doping, expensive annealing techniques, and high thermal budgets for the creation of source and the drain regions in consequence of which the fabrication complexity of the TFET structure reduces.…”

Section: Introductionmentioning

confidence: 99%

Performance investigation of asymmetric double‐gate doping less tunnel FET with Si/Ge heterojunction

Sharma

Kaur

2020

IET Circuits, Devices & Systems

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Tunnel field effect transistors (TFETs) have been exhibiting an enticing performance to succeed in metal-oxidesemiconductor technology. However, TFET also possesses several challenges such as low drive current, ambipolarity, and requirement of abrupt doping profiles for the occurrence of band-to-band tunnelling (BTBT) conduction mechanism at the junction. To overcome these challenges, the authors propose a heterojunction doping less tunnel field-effect transistor with an asymmetric double gate (HJ ADG DLTFET). This device employs a low bandgap material at the source region, which increases the BTBT rate at the channel-source interface leading to enhanced drive current while maintaining low off-current. Consequently, an increment of one order for I ON (∼1.5 × 10 −5 A/µm) compared to the conventional ADG DLTFET has been provided by this device. Additionally, the comparative analysis of the proposed device and conventional one has been performed to reveal the advantages of the proposed structure in terms of transfer characteristics, transconductance, gate-todrain capacitance, cutoff frequency, gain-bandwidth product, device efficiency, and transconductance frequency product. Moreover, the effect of gate length and drain voltage variations has been analysed for HJ ADG DLTFET concerning the aforementioned characteristics.

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Section: Introductionmentioning

confidence: 99%

Performance investigation of asymmetric double‐gate doping less tunnel FET with Si/Ge heterojunction

Sharma

Kaur

2020

IET Circuits, Devices & Systems

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“…Moreover, to exploit full benefits of this concept, configurable BJT have also been built to exhibit switching between n-i-n to p-ip and vice versa [7] [8]. Hence, due to polarity control, problems associated with CP concept in BJT devices have now been resolved, and also have opened the integration possibility with other devices [9] [10] [11]. However, β of PC based devices are very poor compared to those devices that are based on CP concept.…”

Section: Introductionmentioning

confidence: 99%

Next Generation Logic Gate Designs using Improved Polarity Control Bipolar Junction Transistor

Bramhane*,

Chede,

Kadbe

et al. 2019

IJRTE

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In this paper, we have proposed a dopingless reconfigurable polarity control bipolar junction transistor (PC-BJT) with enhanced current gain and currentoff frequency. It can be used as both n-i-n or p-i-p type transistors by applying an appropriate voltage (±1 V) on its polarity control electrodes. It is very first time that BJTs are used to implemented in XOR logic gate design with the concepts of reconfigurability and polarity control electrodes. For this, a new symbol is introduced to demonstrate the behavior of logic gates. Moreover, series and parallel combination of the proposed device exhibits the behavior of two-input NAND-NOR (PC=+1 V) and AND-OR (PC=-1 V) gates. Moreover, the proposed device exhibits the low on-time voltage and improved breakdown voltage compared to the conventional PC-BJT.

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“…By work-function engineering and present of N + layer at S/C region will improves ON state current, SS and threshold voltage (Vth), but JL-TFET also suffer from doping restrictions which are like RDFs and fabrication complexity. So, to solve these problems doping less TFET based on charge plasma (CP-TFET) [12][13][14][15] and electrically doped (ED-TFET) [16][17][18][19][20] ideas have been introduced. Both CP-TFET and ED-TFET provides low fabrication complexity and low-cost thermal budget.…”

Section: Introductionmentioning

confidence: 99%

Approach on electrically doped TFET for suppression of ambipolar and improving RF performance

Chandan

Nigam

Sharma

2019

IET Circuits, Devices & Systems

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In this editorial, the effect of dual gate underlap has been implemented on ED-TFET and it is named as underlap dual metal gate electrically doped tunnel FET (UL-DMG-ED-TFET). The proposed device has been reviewed in terms of device characteristics and analogue/radio-frequency figure of metrics. By using underlap theory, the authors have resolved the issues of ambipolarity and gate leakage current but somewhat C gd also increases without affecting the DC performances. Moreover, the authors have implemented the dual gate on the proposed device which helps to improve the DC and RF FOMs. Furthermore, the inversion layer and C gd inversion along with parasitic capacitances also deliberate on proposed device (UL-DMG-ED-TFET). Finally, the dual gate-underlap provides better DC and analogue/RF performances in comparison over conventional structure.

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PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET

Cited by 69 publications

References 25 publications

Performance investigation of asymmetric double‐gate doping less tunnel FET with Si/Ge heterojunction

Performance investigation of asymmetric double‐gate doping less tunnel FET with Si/Ge heterojunction

Next Generation Logic Gate Designs using Improved Polarity Control Bipolar Junction Transistor

Approach on electrically doped TFET for suppression of ambipolar and improving RF performance

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