Robust SRAM Designs and Analysis

Modelling and simulation of SEU in bulk Si and Ge SRAM

“…1) in retention (hold) mode. From these curves, it is possible to extract the Static Noise Margin (SNM) that graphically corresponds to the diagonal of the largest square that fits within the back-to-back DC characteristics of the two inverters [13]. Results show that the SNM for the Ge-based SRAM is +11% higher than the SNM extracted for the Si-based SRAM.…”

Leakage Analysis of a Low Power 10 Transistor SRAM Cell in 90 nm Technology

“…Subthreshold operation holds promise for ultra-low power operation of these emerging applications. Due to scaling of device dimensions, random variations in Process, Supply Voltage and Temperature (PVT) poses major challenges to the high performance circuits and system design [1]- [3]. The random fluctuations are much pronounced in smallest-geometry devices usually used in area-constraint circuits such as SRAM cells [7].…”

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“…It also provided an idea to build an array of required size. [4]. It furnishes a systematic and a complete view of SRAM bit cell circuits, architectures, and design and analysis techniques [4].…”

“…[4]. It furnishes a systematic and a complete view of SRAM bit cell circuits, architectures, and design and analysis techniques [4]. This book is indeed a great help for VLSI design engineers to design SRAM and cache architecture reasonably [4].…”

“…It furnishes a systematic and a complete view of SRAM bit cell circuits, architectures, and design and analysis techniques [4]. This book is indeed a great help for VLSI design engineers to design SRAM and cache architecture reasonably [4]. This book aided me in understanding the theoretical background of all the peripherals of an SRAM and also came across the different topologies of low power SRAMs and their classifications based on the robustness.…”