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Reliability testing, namely receiver autonomous integrity monitoring (RAIM), consists of statistical testing of least-squares residuals of observations, e.g., on an epoch-by-epoch basis aiming towards reliable navigation fault detection and exclusion (FDE). In this paper, classic RAIM and FDE methods are extended with testing of range-rate residuals to find inconsistent velocity solutions in order to contribute to the reliability of the system with special focus on degraded signal environments. Reliability enhancement efforts discussed include a Backward-FDE scheme based on statistical outlier detection and an iteratively reweighted robust estimation technique, a modified Danish method. In addition, measurement weighting assigned to code and Doppler observations is assessed in the paper in order to allow fitting a priori variance models to the estimation processes. The schemes discussed are also suitable in terms of computational convenience for a combined GPS/ Galileo system. The objective of this paper is to assess position and velocity reliability testing and enhancement in urban and indoor conditions and to analyze the navigation accuracy conditions with high sensitivity GPS (HSGPS) tests. The results show the necessity of weighted estimation and FDE for reliability enhancement in degraded signalenvironment navigation.

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Abstract. Transport Triggered Architecture (TTA) offers a cost-effective tradeoff between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complexvalued fast Fourier transform (FFT). The proposed processor consumes only 1.55 µJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.

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In this paper, we describe a processor architecture tailored for radix-4 and mixed-radix FFT algorithms, which have lower arithmetic complexity than radix-2 algorithms. The processor is based on transport triggered architecture and several optimizations have been used to improve the energy-efficiency. The processor has been synthesized on a 130nm standard cell technology and analysis show that a programmable solution can possess energy-efficiency comparable to a fixed-function ASIC.

In this paper, an array processor architecture for 2-D discrete cosine transform (DCT) based on the row-column decomposition of the 2-D DCT. The utilized I-D DCT architectures are derived by applying the principles used to construct pipelined fast Fourier transform architectures. In general, this approach has not been used due to the irregularities found in the fast DCT algorithms. The basis of our architectural derivation is the constant geometry fast algorithms for DCT described earlier. By rescheduling the operations, an in-place algorithm can be obtained, which can be mapped onto a pipelined structure with the aid of vertical projection. In addition, a sequential matrix transposition network is described, which is based on shift-exchange units.

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