In the advent of very high data rates of the
upcoming 3G long-term evolution telecommunication systems,
there is a crucial need for efficient and flexible turbo decoder
implementations. In this study, a max-log-MAP turbo decoder is
implemented as an application-specific instruction-set processor.
The processor is accompanied with accelerating computing units,
which can be controlled in detail. With a novel memory interface,
the dual-port memory for extrinsic information is avoided. As a
result, processing one trellis stage with max-log-MAP algorithm
takes only 1.02 clock cycles on average, which is comparable to
pure hardware decoders. With six turbo iterations and 277 MHz
clock frequency 22.7 Mbps, decoding speed is achieved on 130 nm technology.
In several digital signal processing algorithms, computational nodes are organized in consecutive stages and data is reordered between these stages. Parallel computation of such algorithms with reduced number of processing elements implies that several computational nodes are assigned to each element. As a drawback, permutations become more complex and require data storage. In this paper, a systematic design methodology for stride permutation networks is derived. These permutations are represented with Boolean matrices, which are decomposed and mapped directly onto register-based networks. The resulting networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the lower bound in the number of registers indicating area-efficiency. Since the proposed methodology is systematic, it can be exploited in automated design generation.
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