In several digital signal processing algorithms, computational nodes are organized in consecutive stages and data is reordered between these stages. Parallel computation of such algorithms with reduced number of processing elements implies that several computational nodes are assigned to each element. As a drawback, permutations become more complex and require data storage. In this paper, a systematic design methodology for stride permutation networks is derived. These permutations are represented with Boolean matrices, which are decomposed and mapped directly onto register-based networks. The resulting networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the lower bound in the number of registers indicating area-efficiency. Since the proposed methodology is systematic, it can be exploited in automated design generation.
Both the matrix inversion and solving a set of linear equations can be computed with the aid of the Cholesky decomposition. In this paper, the Cholesky decomposition is mapped to the typical resources of digital signal processors (DSP) and our implementation applies a novel way of computing the fixed-point inverse square root function. The presented principles result in savings in the number of clock cycles. As a result, the Cholesky decomposition can be incorporated in applications such as 3G channel estimator where short execution time is crucial.
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