Multi-port interconnection networks for radix-R algorithms

Takala, Jarmo; Jarvinen, T.; Salmela, Perttu; Akopian, David

doi:10.1109/icassp.2001.941133

Cited by 12 publications

(20 citation statements)

References 11 publications

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“…The slice and BRAM utilizations are extracted after synthesis and mapping. 4 The cycle times used to compute the latency are extracted after place-and-route.…”

Section: Discussionmentioning

confidence: 99%

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Automatic generation of customized discrete fourier transform IPs

Nordin

Milder

Hoe

et al. 2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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This paper presents a parameterized soft core generator for the discrete Fourier transform (DFT). Reusable IPs of digital signal processing (DSP) kernels are important time-saving resources in DSP hardware development. Unfortunately, reusable IPs, however optimized, can introduce inefficiencies because they cannot fit the exact requirements of every application context. Given the well-understood and regular computation in DSP kernels, an automatic tool can generate high-quality ready-to-use IPs customized to user-specified cost/performance tradeoffs (beyond basic parameters such as input size and data format). The paper shows that the generated DFT cores can match closely the performance and cost of DFT cores from the Xilinx LogiCore library. Furthermore, the generator can yield DFT cores over a range of different performance/cost tradeoff points that are not available from the library.

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“…The slice and BRAM utilizations are extracted after synthesis and mapping. 4 The cycle times used to compute the latency are extracted after place-and-route.…”

Section: Discussionmentioning

confidence: 99%

“…More 3 The generator can also produce a "bit-reversed-in, natural-out" variation. 4 A slice is the basic logic building block in Virtex FPGAs. Each slice has two SRAM-based 4-to-1 lookup tables and two 1-bit registers.…”

Section: Discussionmentioning

confidence: 99%

Automatic generation of customized discrete fourier transform IPs

Nordin

Milder

Hoe

et al. 2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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“…However, Ma's scheme is developed for an FFT core that involves a single butterfly unit, so the overall approach is limited in terms of throughput improvement. Nordin et al [4] presented a parameterized soft core generator for the FFT based on the Peace FFT algorithm with the stride permutation approach proposed by Takala et al [5]. By running multiple butterflies simultaneously with a scalable stride permutation, the generated FFT achieves an effective balance between hardware costs and performance features, and is also customizable based on given design constraints.…”

Section: Background and Related Workmentioning

confidence: 99%

Systematic generation of FPGA-based FFT implementations

Kee

Petersen

Kornerup

et al. 2008

2008 IEEE International Conference on Acoustics, Speech and Signal Processing

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In this paper, we propose a systemic approach for synthesizing field-programmable gate array (FPGA) implementations of fast Fourier transform (FFT) computations. Our approach considers both cost (in terms of FPGA resource requirements), and performance (in terms of throughput), and optimizes for both of these dimensions based on user-specified requirements. Our approach involves two orthogonal techniques -FFT inner loop unrolling and outer loop unrolling -to perform design space exploration in terms of cost and performance. By appropriately combining these two forms unrolling, we can achieve cost-optimized FFT implementations in terms of FPGA slices or block RAMs in FPGA, subject to the required throughput. We compared the results of our synthesis approach with a recently-introduced commercial FPGA intellectual property (IP) core -the FFT IP module in the Xilinx LogiCore Library, which provides different FFT implementations that are optimized for a limited set of performance levels. Our results demonstrate efficiency levels that are in some cases better than these commercial IP blocks. At the same time, our approach provides the advantages of being able to optimize implementations based on arbitrary, user-specified performance levels, and of being based on general formulations of FFT loop unrolling trade-offs, which can be retargeted to different kinds of FPGA devices.

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“…Compared to earlier designs, the networks result in smaller complexity in terms of multiplexers and registers. The lower bound on register complexity for stride permutations is derived and shown to be equal to the register complexity of the proposed networks, contrary to earlier proposals in [8]. In addition, the supported strides have been extended from [9], where only matrix transposes were covered.…”

Section: Introductionmentioning

confidence: 98%

Stride Permutation Networks for Array Processors

Jarvinen

Salmela

Sorokin

et al. 2007

J VLSI Sign Process Syst Sign Im

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In several digital signal processing algorithms, computational nodes are organized in consecutive stages and data is reordered between these stages. Parallel computation of such algorithms with reduced number of processing elements implies that several computational nodes are assigned to each element. As a drawback, permutations become more complex and require data storage. In this paper, a systematic design methodology for stride permutation networks is derived. These permutations are represented with Boolean matrices, which are decomposed and mapped directly onto register-based networks. The resulting networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the lower bound in the number of registers indicating area-efficiency. Since the proposed methodology is systematic, it can be exploited in automated design generation.

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Multi-port interconnection networks for radix-R algorithms

Cited by 12 publications

References 11 publications

Automatic generation of customized discrete fourier transform IPs

Automatic generation of customized discrete fourier transform IPs

Systematic generation of FPGA-based FFT implementations

Stride Permutation Networks for Array Processors

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