Stride Permutation Networks for Array Processors

Jarvinen, T.; Salmela, Perttu; Sorokin, Harri; Takala, Jarmo

doi:10.1007/s11265-006-0031-8

Cited by 13 publications

(11 citation statements)

References 20 publications

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“…Each has one read port and one write port. 1 Memory arrays M 0 and M 1 are connected to lookup tables R and W (respectively), which hold pre-computed address values.…”

Section: Parameterized Datapathmentioning

confidence: 99%

“…As discussed in Section VI, [2] provides a generation technique for a subset of streaming permutations. Other approaches (e.g., [1]) consider streaming implementations of a specific family (stride permutations). [12] builds streaming permutation structures using a register allocation method, resulting in a large number of individual registers connected with switches or multiplexers.…”

Section: Related Workmentioning

confidence: 99%

“…For example, [1] gives a method to design streaming implementations of one family of permutations called stride permutations. [2] expands on this significantly, but its technique is still not general; its method only applies to a specific family of permutations, and only when n and w are powers of two.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Automatic generation of streaming datapaths for arbitrary fixed permutations

Milder¹,

Hoe²,

Puschel³

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-This paper presents a technique to perform arbitrary fixed permutations on streaming data. We describe a parameterized architecture that takes as input n data points streamed at a rate of w per cycle, performs a permutation over all n points, and outputs the result in the same streaming format. We describe the system and its requirements mathematically and use this mathematical description to show that the datapaths resulting from our technique can sustain a full throughput of w words per cycle without stalling. Additionally, we provide an algorithm to configure the datapath for a given permutation and streaming width.Using this technique, we have constructed a full synthesis system that takes as input a permutation and a streaming width and outputs a register-transfer level Verilog description of the datapath. We present an evaluation of our generated designs over varying problem sizes and streaming widths, synthesized for a Xilinx Virtex-5 FPGA.

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“…Each has one read port and one write port. 1 Memory arrays M 0 and M 1 are connected to lookup tables R and W (respectively), which hold pre-computed address values.…”

Section: Parameterized Datapathmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Automatic generation of streaming datapaths for arbitrary fixed permutations

Milder¹,

Hoe²,

Puschel³

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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show abstract

“…A stride-by-2 s permutation [5], [7] is a circular permutation of s bits to the left, and it can be expressed as a composition of s perfect shuffles:…”

Section: A Types Of Bit-dimension Permutationsmentioning

confidence: 99%

Optimum Circuits for Bit-Dimension Permutations

Garrido

Grajal

Gustafsson

2019

IEEE Trans. VLSI Syst.

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In this paper we presents a systematic approach to design hardware circuits for bit-dimension permutations. The proposed approach is based on decomposing any bit-dimension permutation into elementary bit-exchanges. Such decomposition is proven to achieve the theoretical minimum number of delays required for the permutation. This offers optimum solutions for multiple well-known problems in the literature that make use of bit-dimension permutations. This includes the design of permutation circuits for the fast Fourier transform (FFT), bit reversal, matrix transposition, stride permutations and Viterbi decoders.

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“…By using register-based commutators, those folded FFT architectures achieve high computational performance per unit area. In [5], the authors propose a register-based stride permutation network for array processor. The proposed network supports any stride of power-of-two and achieves a high area efficiency by approaching the lower bound in the number of registers.…”

Section: Introductionmentioning

confidence: 99%

Energy-efficient architecture for stride permutation on streaming data

Ren

Prasanna

2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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Abstract-Stride permutation is widely used in various digital signal processing algorithms when implementing on FPGAs. Permuting a long data sequence through hardware wiring leads to high area consumption and routing complexity. A more scalable approach is to build a hardware structure to permute streamed data inputs. In this paper, we present an energy-efficient architecture to perform stride (power-of-two) permutation on streaming data. A three-stage structure, composed of two stages of interconnection networks and one stage of data buffers, is used as a baseline architecture. To improve the energy efficiency, we develop a data remapping technique to reduce the memory consumed by the data buffers. This technique can be used to reduce the required memory by 50% at the expense of small amount of extra logic. We also present a multiplexer-based cyclic shift interconnection network designed for low power purpose. Our proposed architecture is evaluated using two performance metrics: the composite Energy×Area×Time (EAT) metric and the energy efficiency defined as points (real number) per Joule. The experimental results show that the proposed data remapping technique reduces up to 40% dynamic power consumption compared with the baseline architecture. The proposed architecture shows a high energy efficiency of up to 75.3 giga points/Joule, and has an EAT ratio of 0.31 to 0.35 over the baseline architecture for various streaming width w(2 ≤ w ≤ 32).

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Stride Permutation Networks for Array Processors

Cited by 13 publications

References 20 publications

Automatic generation of streaming datapaths for arbitrary fixed permutations

Automatic generation of streaming datapaths for arbitrary fixed permutations

Optimum Circuits for Bit-Dimension Permutations

Energy-efficient architecture for stride permutation on streaming data

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