2019
DOI: 10.1109/tvlsi.2019.2892322
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Optimum Circuits for Bit-Dimension Permutations

Abstract: In this paper we presents a systematic approach to design hardware circuits for bit-dimension permutations. The proposed approach is based on decomposing any bit-dimension permutation into elementary bit-exchanges. Such decomposition is proven to achieve the theoretical minimum number of delays required for the permutation. This offers optimum solutions for multiple well-known problems in the literature that make use of bit-dimension permutations. This includes the design of permutation circuits for the fast F… Show more

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Cited by 22 publications
(42 citation statements)
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References 32 publications
(52 reference statements)
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“…The number of delays (D), the number of multiplexers (M ) and the latency (Lat) of circuits that calculate an elementary bit exchange are summarized in Table I. This table is brought from [2] and the description of the circuits can be found in [2], [13]. The circuits for elementary bit-exchange are classified into circuits that exchange two serial dimensions, i.e., serialserial (ss), two parallel dimensions, i.e., parallel-parallel (pp)…”
Section: A Elementary Bit-exchangementioning
confidence: 99%
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“…The number of delays (D), the number of multiplexers (M ) and the latency (Lat) of circuits that calculate an elementary bit exchange are summarized in Table I. This table is brought from [2] and the description of the circuits can be found in [2], [13]. The circuits for elementary bit-exchange are classified into circuits that exchange two serial dimensions, i.e., serialserial (ss), two parallel dimensions, i.e., parallel-parallel (pp)…”
Section: A Elementary Bit-exchangementioning
confidence: 99%
“…Regarding the storage elements, each ss permutation can be carried out either by a memory or by a circuit for serial-serial permutation [2], [4]. The latter consists of a buffer and two multiplexers.…”
Section: Previous Approaches For Parallel Bit Reversalmentioning
confidence: 99%
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