This paper presents a set of novel two-parallel pipelined fast Fourier transform architectures for discrete Fourier transform computation of real-valued signal. The previous approaches of designing real-valued fast Fourier transform (RFFT) architectures are the attempts made to make the data path real. Some of the previous designs have partial real data paths (only first two stages are real), whereas the other designs have complete real data-paths, but reordering registers are required to bring the real and imaginary parts in parallel. Hence, these approaches reduce the number of registers and butterflies only to some extent in the RFFT design. In the proposed designs, feedback-based scheduling structures are introduced, which reduce the number of registers to half in several stages when compared with the previously known designs. Therefore, the proposed designs require 30% less area and 31.5% less power than the prior designs.
In this Letter, a reconfigurable processing element (PE) for pipelined SDF FFT architecture is presented, which can be configured to compute 2, 3 and 5-point DFTs. Foremost, the proposed PE architecture for the 5-point DFT computation is designed by factorising the 5-point DFT computation operation into 2 × 2 cyclic convolution units and then the 2-and 3-point DFTs structures are mapped on to it using multiplexers. Thus, all three configurations are possible. In the case of prior 5-point PE designs, the PE can start its operation only after the arrival of all the five-input data, whereas the proposed PE completes a part of computation after the arrival of the first three inputs and reuse the same hardware to process the next two inputs. As a result, the proposed PE requires less hardware, at the same time, preserving the throughput of prior PE. The proposed PE required 25% less multiplier and one adder less compared to the Winograd algorithm based 5-input PE.
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