Pipelined FFT architectures for real-time signal processing and wireless communication applications

Glittas, Antony Xavier; Lakshminarayanan, G.

doi:10.1109/isvdat.2014.6881052

Cited by 5 publications

(4 citation statements)

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“…In the modified DFG, excluding the first stage all other stages have N/4 butterflies instead of N/2. Several architectures [16][17][18][19][20][21][22] are proposed to evaluate this modified DFG. However, many real-time and mobile applications require compact and low-power consuming RFFT architecture.…”

Section: Introductionmentioning

confidence: 99%

“…These requirements are satisfied by the two-parallel RFFT architecture. Though some two-parallel RFFT architectures are already proposed in [17][18][19][20]22], these architectures have certain major disadvantages in terms of hardware complexity.…”

Section: Introductionmentioning

confidence: 99%

“…In [17, 18, 22], the first two stages of two‐parallel RFFT architecture are realised with real data path because the computations in the first two stages of the RFFT DFG are real (i.e. there is no imaginary part).…”

Section: Introductionmentioning

confidence: 99%

“…there is no imaginary part). As a result, the architectures in [17, 18, 22] have real butterfly units and real delay commutator units in the first two stages. The hardware implementation cost of complex data path is equal to twice the hardware implementation cost of real data path because word length of complex data path is twice that of real data path.…”

Section: Introductionmentioning

confidence: 99%

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Two‐parallel pipelined fast Fourier transform processors for real‐valued signals

Glittas

Sellathurai

Lakshminarayanan

2016

IET Circuits, Devices & Systems

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This paper presents a set of novel two-parallel pipelined fast Fourier transform architectures for discrete Fourier transform computation of real-valued signal. The previous approaches of designing real-valued fast Fourier transform (RFFT) architectures are the attempts made to make the data path real. Some of the previous designs have partial real data paths (only first two stages are real), whereas the other designs have complete real data-paths, but reordering registers are required to bring the real and imaginary parts in parallel. Hence, these approaches reduce the number of registers and butterflies only to some extent in the RFFT design. In the proposed designs, feedback-based scheduling structures are introduced, which reduce the number of registers to half in several stages when compared with the previously known designs. Therefore, the proposed designs require 30% less area and 31.5% less power than the prior designs.

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