Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform

Pitkänen, Teemu; Makinen, R.; Heikkinen, J.; Partanen, Tero; Takala, Jarmo

doi:10.1007/11796435_24

Cited by 21 publications

(16 citation statements)

References 13 publications

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“…Clock gating technique can be used to reduce the power consumption of non active function units. Significant saving can be expected on units with low utilization But the clock gating technique also suffers from performance loss [10].…”

Section: Application Analysis and Asynchronous Function Unitsmentioning

confidence: 99%

A Low-Power Application Specific Instruction Set Processor Using Asynchronous Function Units

Wang

Dai

2007

7th IEEE International Conference on Computer and Information Technology (CIT 2007)

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Low-power design became crucial with widespread use of the embedded systems. The embedded processors need to be efficient in order to achieve real-time requirements with low power consumption for specific algorithms. As the superset of traditional very long instruction word (VLIW) architecture, the main advantages of Transport Triggered Architecture (TTA) are its simplicity and flexibility. In TTA processors, the special function units can be utilized to increase performance or reduce power dissipation. Asynchronous circuits have characteristic of low power consumption and it is possible to exploit this characteristic to design embedded processors. In this article, we designed a low-power embedded processor using asynchronous function units. The processor core is globally synchronous and locally asynchronous implementation using not only synchronous function units but also asynchronous function units. We also presented an efficient design flow that use asynchronous circuits in TTA framework, which is only a synchronous design environment. The test result shows that this processor has lower power dissipation than its pure synchronous version that only uses synchronous function units.

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Section: Application Analysis and Asynchronous Function Unitsmentioning

confidence: 99%

A Low-Power Application Specific Instruction Set Processor Using Asynchronous Function Units

Wang

Dai

2007

7th IEEE International Conference on Computer and Information Technology (CIT 2007)

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“…The reference ASIP was a processor core tailored for radix-4 FFT computations described in [18]. The processor is based on transport triggered architecture (TTA).…”

Section: Reference Asip With Dual-port Memorymentioning

confidence: 99%

Parallel Memory Architecture for Application-Specific Instruction-Set Processors

Pitkänen

Tanskanen

Makinen³

et al. 2008

J Sign Process Syst Sign Image Video Technol

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Many of the current applications used in battery powered devices are from digital signal processing, telecommunication, and multimedia domains. These applications typically set high requirements for computational performance and often parallelism is the key solution to meet the performance requirements. In order to exploit the parallel processing units, memory should be able to feed the data path with data. This calls for a memory organization supporting parallel memory accesses. In this paper, a conflict resolving parallel data memory system for application-specific instruction-set processors is described. The memory structure is generic and reusable to support various application-specific designs. The proposed memory system does not employ any predefined access format signals for memory addressing. The proposed parallel memory system is attached to an application-specific instruction-set processor core and comparison on area, power, and critical path are shown. The experiments show that significant power savings can be obtained by exploiting the parallel memory system instead of multiport memory.

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“…Several optimizations have been used to improve the energy-efficiency of the processor. This paper is based on the principles reported in our earlier papers [18,19,21] and shows that a programmable solution can possess energy-efficiency comparable to fixed-function ASIC. The processor is tailored for radix-4 and mixed-radix FFT algorithms and supports several transform lengths.…”

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confidence: 98%