Low-Power Application-Specific Processor for FFT Computations

Pitkänen, Teemu; Takala, Jarmo

doi:10.1007/s11265-010-0528-z

Cited by 15 publications

(4 citation statements)

References 24 publications

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“…The processor was designed using a transport triggered architecture (TTA) template [8]. It improves a previous FFT processor [9] by further increasing its energy-efficiency. Several optimizations were applied to allow compressing the computation kernel into only one -repeatedly executed -instruction word that can be executed in a more energy-efficient way.…”

Section: Introductionmentioning

confidence: 99%

Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture

Žádník,

Takala

2019

Preprint

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This paper describes a low-power processor tailored for fast Fourier transform computations where transport triggering template is exploited. The processor is software-programmable while retaining an energy-efficiency comparable to existing fixed-function implementations. The power savings are achieved by compressing the computation kernel into one instruction word. The word is stored in an instruction loop buffer, which is more power-efficient than regular instruction memory storage. The processor supports all power-oftwo FFT sizes from 64 to 16384 and given 1 mJ of energy, it can compute 20916 transforms of size 1024.

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Section: Introductionmentioning

confidence: 99%

Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture

Žádník,

Takala

2019

Preprint

Self Cite

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“…Thus, design of an efficient FFT processor is of great significance in meeting the requirements of real-time applications in terms of speed, accuracy, low cost, and a smaller chip area. The FFT algorithm is mainly implemented on field-programmable gate arrays (FPGAs) [10][11][12], which offer advantages such as higher performance, less design time, and lower costs than digital signal processor-based systems (DSPs) [13][14][15]. Moreover, the increasing gate density of FPGAs in recent years has enabled designers to implement data-parallel signal processing algorithms by using massively parallel architectures that can meet high-speed processing requirements; this has resulted in implementations on FPGA that deliver outstanding performance in many applications.…”

Section: Introductionmentioning

confidence: 99%

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

et al. 2018

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Abstract:The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of rotary machines. The complexity and cost of the associated hardware limit the use of FFT in real-time applications. In this paper, an efficient hardware architecture for FFT implementation is proposed based on the radix-2 decimation in frequency algorithm (R2DIF) and a feedback pipelined technique (FB) that allows effective sharing of storage between the input and output data at each stage of the FFT process via shift registers. The proposed design uses an optimal hybrid rotation scheme by combining the modified coordinate rotation digital computer (m-CORDIC) algorithm and a binary encoding technique based on canonical signed digit (CSD) for replacing the complex multipliers in FFT. The m-CORDIC algorithm, with an adaptive iterative monitoring process, improves the convergence of computation, whereas the CSD algorithm optimizes the multiplication of constants using a simple shift-add method. Therefore, the proposed design does not require the large memory typically entailed by existing designs to carry out twiddle factor multiplication in large-point FFT implementations, thereby reducing its area on the chip. Moreover, the proposed pipelined FFT processor uses only distributed logic resources and does not require expensive dedicated functional blocks. Experimental results show that the proposed design outperforms existing state-of-the-art approaches in speed by about 49% and in resource utilization by around 51%, while delivering the same accuracy and utilizing less chip area.

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“…In the past, a large number of power management techniques have been proposed in the literature. These techniques differ in the following aspects: a) the level of the design hierarchy at which power is addressed (e.g., manufacturing techniques at the lowest level and system level (i.e., multiple components in a system) techniques at the highest level of the design hierarchy) b) the development phase at which they are incorporated into the system (design, fabrication, or run time), c) the power equation parameter(s) used to optimize power/performance, and d) the power [3,32] V DD , f DYNA ARCH DESN Specialized Accelerator [33] C ef f , N clk , f DYNA ARCH DESN multicore / many-core [11,34,35,36,37,38] C ef f , f DYNA ARCH DESN heterogeneous components [11,34,35,36,37,38] Power consumption on a CPU or GPU has two components: 1) the dynamic power:…”

Section: Low-power Design Techniquesmentioning

confidence: 99%

“…Some of these techniques can be applied at runtime, while others are design time techniques. Power and energy-efficient cache and scratchpad design [22,23,24,25,26], specialized accelerators [33], multicore (many-core), and heterogeneous computing frameworks [11,34,35,36,37,38] are among the architectural design techniques for reducing dynamic power consumption. Lastly, DVFS [12,13,14,15,16] is an algorithm/system level technique that aims to reduce dynamic power consumption at runtime by changing voltage and/or operating frequency.…”

Section: Low-power Design Techniquesmentioning

confidence: 99%

Dynamic voltage and frequency scaling for 3D graphics applications on the state-of-the-art mobile GPUs

Farazmand¹

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AHB Advanced High-performance Bus. System bus definition within the AMBA 2.0 specification.Defines a high-performance bus including pipelined access, bursts, split, and retry operations. DVFS Dynamic Voltage and Frequency Scaling. Group of algorithms that change voltage and frequency at runtime according to workload to make a trade-off between performance and energy consumption DDR Double Data Rate memory. DDR refers to a specific type of dynamic memory technology, which is synonymous with the dynamic memory used as the global (volatile) memory in computing elements. DOU Days Of Use. For a mobile device, the length of the time from a full battery (re)charge to when the battery dies and requires another recharge. It is often used by different vendors with a predefined set of dashboard tests they use to define their target energy consumption requirements. These requirements are used to drive the design, measure the success of the design, and compare competing designs and platforms. CPU Central Processing Unit. GPU Graphics Processing Unit. GPGPU General-Purpose computing on GPU. There are a number of general-purpose (nongraphics) applications that can benefit significantly from the parallelism offered by graphics processors in terms of performance. GPGPU refers to the concept of running general-purpose (nongraphics) applications on GPUs. OPP Operating Performance Point. A unique permutation of all the frequency domains controlled by DCVS. In this thesis, it refers to the (GPU,DDR) frequency pair. IC Integrated Circuit. PMIC Power Management Interface Controller. The component within of a digital electronic chipset that controls the power distribution and protects the circuit from permanent damage, or data corruption due to voltage droop. It is also in charge of optimizing power distribution to increase battery efficiency. IoE Internet of Everything. IoT Internet of Things. SoC System on a Chip. Refers to the integration of multiple different electronic elements including processors and memories on a single chip in a single fabrication process API Application Programming Interface. A set of well-defined functions that specify the interface of a library with other software components. External components and interact with and use the library by calling its API functions. API only specifies the format of the functions and their behavior as seen by outside entity. It does not expose internal implementation of those behaviors.ix UMD User Mode Driver. A device driver that runs in user-mode in the operating system and acts as the interface between an application and a device driver. IO Input/Output. ADB Android Debug Bridge. Set of command line tools available for the Android operating system, which are used for debugging android operating system and applications. ADB is also used for automation tasks such as starting and stopping applications.

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Low-Power Application-Specific Processor for FFT Computations

Cited by 15 publications

References 24 publications

Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture

Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

Dynamic voltage and frequency scaling for 3D graphics applications on the state-of-the-art mobile GPUs

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