A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

Abstract

Abstract:The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of rotary machines. The complexity and cost of the associated hardware limit the use of FFT in real-time applications. In this paper, an efficient hardware architecture for FFT implementation is proposed based on the radix-2 decimation in frequency algorithm (R2DIF) and a feedback pipelined technique (FB) that allows effective sharing of storage between the input and output data at each stage of the FFT process via shift registers. The proposed design uses an optimal hybrid rotation scheme by combining the modified coordinate rotation digital computer (m-CORDIC) algorithm and a binary encoding technique based on canonical signed digit (CSD) for replacing the complex multipliers in FFT. The m-CORDIC algorithm, with an adaptive iterative monitoring process, improves the convergence of computation, whereas the CSD algorithm optimizes the multiplication of constants using a simple shift-add method. Therefore, the proposed design does not require the large memory typically entailed by existing designs to carry out twiddle factor multiplication in large-point FFT implementations, thereby reducing its area on the chip. Moreover, the proposed pipelined FFT processor uses only distributed logic resources and does not require expensive dedicated functional blocks. Experimental results show that the proposed design outperforms existing state-of-the-art approaches in speed by about 49% and in resource utilization by around 51%, while delivering the same accuracy and utilizing less chip area.

Design optimisation of multiplier‐free parallel pipelined FFT on field programmable gate array

“…Nguyen et al [21] suggested a R2DIF algorithm. In this algorithm, the shift registers were utilised to share data between the input and output ports in a feedback pipeline method.…”

Data-Adaptive Coherent Demodulator for High Dynamics Pulse-Wave Ultrasound Applications

“…After demodulation, the I/Q components are processed through spectral estimation to detect f d . The spectral analysis is performed through the efficient Fast Fourier Transform (FFT) [25][26][27] or more sophisticated adaptive estimators [28][29][30]. The demodulated ultrasound echoes are typically organized in the memory of the processing system along the columns of a matrix.…”

Efficient and Accurate CORDIC Pipelined Architecture Chip Design Based on Binomial Approximation for Biped Robot

“…Therefore, it is possible to compute moving distances and rotation angles of robotic systems in a short time. Recently, energy-efficiency/area-efficiency strategy was the crucial methodology in hardware design [7][8][9][10][11]. In [7], an energy-efficiency design of an image processing technique was proposed for wireless sensor networks.…”

“…An area-efficient, two-dimensional interpolation architecture based on cubic convolution was proposed in [10], which was developed to calculate the square-root function. In [11], the authors proposed an efficient hardware architecture for fast-Fouriertransform (FFT) implementation where the modified CORDIC (m-CORDIC) algorithm was employed to replace the complex multipliers to reduce complexity significantly.…”