Design optimisation of multiplier‐free parallel pipelined FFT on field programmable gate array

Kumar, G. Prasanna; Krishna, B. T.; Kotipalli, Pushpa

doi:10.1049/iet-cds.2019.0512

Cited by 5 publications

(3 citation statements)

References 30 publications

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“…In the FFT algorithm, if the input is assumed to be real, and in the interval [−1,1), the output is in the interval [−N, N). In practice, it can be expressed as FPX (16,14). To prevent data overflow and ensure the accuracy of data, 16-bit truncation is used in the final output butterfly stage.…”

Section: Analysis Of Experimental Resultsmentioning

confidence: 99%

High performance and resource efficient FFT processor based on CORDIC algorithm

Zhao

Liu

et al. 2022

EURASIP J. Adv. Signal Process.

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Fast Fourier Transform is widely used in communication and signal processing. I propose an improved multipath delay commutator pipelining architecture based on the radix-2 time decimation algorithm. By optimizing the intermediate data processing process and the first stage of pipelining, the architecture improves the system's computing speed and reduces the use of registers. I propose a multiplication scheme based on CORDIC and binary decomposition coding to realize complex number multiplication and constant multiplication and to eliminate the use of a multiplier. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations.

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Section: Analysis Of Experimental Resultsmentioning

confidence: 99%

High performance and resource efficient FFT processor based on CORDIC algorithm

Zhao

Liu

et al. 2022

EURASIP J. Adv. Signal Process.

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“…Parallel pipelined FFT requires less electricity due to lower frequency. FFT uses improved Coordinate Rotation Digital Computer (CORDIC) to build FPGA [24,25]. The expanded optimum CORDIC technique demands a lot of math in the initial step.…”

Section: Proposed Reconfigurable Fftmentioning

confidence: 99%

Reconfigurable Logic Design of CORDIC Based FFT Architecture for 5G Communications

Thiruvengadam¹,

Palanivelan²

2023

Intelligent Automation &Amp; Soft Computing

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There are numerous goals in next-generation cellular networks (5G), which is expected to be available soon. They want to increase data rates, reduce end-to-end latencies, and improve end-user service quality. Modern networks need to change because there has been a significant rise in the number of base stations required to meet these needs and put the operators' low-cost constraints to the test. Because it can withstand interference from other wireless networks, and Adaptive Complex Multicarrier Modulation (ACMM) system is being looked at as a possible choice for the 5th Generation (5G) of wireless networks. Many arithmetic units need to be used on the hardware side of multicarrier systems to do the pulse-shaping filters and inverse FFT. The main goal of this study is to adapt complex multicarrier modulation (ACMM) for baseband transmission with low complexity and the ability to change it. We found that this is the first reconfigurable architecture that lets you choose how many subcarriers a subband has while still having the same amount of hardware resources as before. Also, under the new design with a single selection line, it selects from a set of filters. The baseband modulating signal is evaluated and tested using a Field-Programmable Gate Array (FPGA) device. This device is available from a commercial source. New technology outperforms current technology in terms of computational complexity, simple design, and ease of implementation. Additionally, it has a higher power spectrum density, spectral efficiency, a lower bit error rate, and a higher peak to average power ratio than existing technology.

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“…A multiplication-free design of an efficient FFT architecture based on the radix-2 decimation in frequency method is indicated in [20]. The complex twiddle factors are replaced by the uniform Montgomery algorithm, which performs shift/addition operations instead of multiplications.…”

Section: Introductionmentioning

confidence: 99%

BFT—Low-Latency Bit-Slice Design of Discrete Fourier Transform

Guaragnella

Giorgio

Rízzí

2023

JLPEA

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Structures for the evaluation of fast Fourier transforms are important components in several signal-processing applications and communication systems. Their capabilities play a key role in the performance enhancement of the whole system in which they are embedded. In this paper, a novel implementation of the discrete Fourier transform is proposed, based on a bit-slice approach and on the exploitation of the input sequence finite word length. Input samples of the sequence to be transformed are split into binary sequences and each one is Fourier transformed using only complex sums. An FPGA-based solution characterized by low latency and low power consumption is designed. Simulations have been carried out, first in the Matlab environment, then emulated in Quartus IDE with Intel. The hardware implementation of the conceived system and the test for the functional accuracy verification have been performed, adopting the DE2-115 development board from Terasic, which is equipped with the Cyclone IV EP4CE115F29C7 FPGA by Intel.

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Design optimisation of multiplier‐free parallel pipelined FFT on field programmable gate array

Cited by 5 publications

References 30 publications

High performance and resource efficient FFT processor based on CORDIC algorithm

High performance and resource efficient FFT processor based on CORDIC algorithm

Reconfigurable Logic Design of CORDIC Based FFT Architecture for 5G Communications

BFT—Low-Latency Bit-Slice Design of Discrete Fourier Transform

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