Low-Power Twiddle Factor Unit for FFT Computation

Low-power application-specific processor for FFT computations

“…Several optimizations have been used to improve the energy-efficiency of the processor. This paper combines results from our previous papers [7,8] and shows that a programmable solution can possess energy-efficiency comparable to fixed-function ASIC. The processor is tailored for radix-4 and mixed-radix FFT algorithms and supports several transform lengths.…”

“…Several methods have been proposed to minimize the lookup tables for generating twiddle factors but mainly for radix-2 algorithms. We have developed a method for minimizing the coefficient tables for radix-4 FFT such that also mixed-radix algorithms are supported and such a twiddle factor unit is described in detail in [8]. For N-point FFT, we need to store N/8 + 1 complex-valued coefficients in a table and four real-valued adders and some control logic are needed to produce the twiddle factors.…”

A novel approach for DFT computation

“…In the broad sense, the DFT of a discrete time signal sequence of length N is analytically expressed as proposed a process to generate the twiddle factor that requires less memory space and also suitable for radix-4 FFT algorithm [19].…”

Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture

“…The generation of twiddle factors is based on a lookup table (LUT) implemented as a single-port synchronous read-only memory (ROM) of pre-computed values. It follows the same approach as the one described in [20]. The address for the LUT ROM is computed from the linear index by a bit permutation and scaling based on the current FFT size.…”