Pipeline architecture for 8×8 discrete cosine transform

Abstract

In this paper, an array processor architecture for 2-D discrete cosine transform (DCT) based on the row-column decomposition of the 2-D DCT. The utilized I-D DCT architectures are derived by applying the principles used to construct pipelined fast Fourier transform architectures. In general, this approach has not been used due to the irregularities found in the fast DCT algorithms. The basis of our architectural derivation is the constant geometry fast algorithms for DCT described earlier. By rescheduling the operations, an in-place algorithm can be obtained, which can be mapped onto a pipelined structure with the aid of vertical projection. In addition, a sequential matrix transposition network is described, which is based on shift-exchange units.

Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor

“…The d jk [8..0] is a 9-bit spatial pixel, where d jk [8] is MSB bit. In (15), Mult is the coarse result of multiplication that is an integer since the floating number is shifted out, so there are serious truncation errors. To reduce the error, the first MSB of the floating number of each section is added to (15) as…”

“…where d jk [n-1] is the first MSB of the floating number to compensate the d jk [8..n] shifting from (15), n=1 to 4. For example, d jk [3] is a maximum floating bit in the last section.…”

“…The transposed cell can be realized with either embedded-RAM or register. With register-based implementation [12,14,15], the circuit design and simulation is easy, but we need large silicon area. Instead, one can employ embedded RAM rather than register to reduce the chip size.…”

“…Clearly, the proposed DCT can reduce the memory cell. For DCT implementation, most of architectures require ROM table to store the cosine coefficients [11][12][13][14][15]. From (7) and (8), we require two sets of 4×4 cosine matrix.…”

“…The bit-by-bit arithmetic approach [14] can reduce the circuit complexity, but the word length would constrain the processing speed. The pipeline architecture [15] is designed to achieve high efficiency for data transposition.…”