Hardware Cost Estimation for Application-Specific Processor Design

Pitkänen, Teemu; Rantanen, T.; Cilio, Andrea G. M.; Takala, Jarmo

doi:10.1007/11512622_23

Cited by 11 publications

(13 citation statements)

References 9 publications

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“…For example, [12], [14] use a simulation based technique for evaluating the performance of TTA-based ASIPs. In their approach, they store the simulationtrace in a database.…”

Section: Methodsmentioning

confidence: 99%

“…Previous research (e.g. [12]- [15]) has shown that this results in fast and reasonably accurate (e.g. less than 10% error for energy [13]) cost estimations.…”

Section: Introductionmentioning

confidence: 94%

“…less than 10% error for energy [13]) cost estimations. To our knowledge however, current estimation tools [12]- [15] require the target applications' simulation traces for computing the delay and active power consumption of a design. This method requires a time-consuming simulation generating the activity traces of the processor's modules.…”

Section: Introductionmentioning

confidence: 99%

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An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors

Jordans

Corvino

Jóźwiak

et al. 2013

2013 Euromicro Conference on Digital System Design

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Design space exploration for ASIP instruction-set design is a very complex problem, involving a large set of architectural choices. Existing methods are usually handcrafted and time-consuming. In this paper, we propose and investigate a rapid method to estimate the energy consumption of candidate architectures for VLIW ASIP processors. The proposed method avoids the time-consuming simulation of the candidate prototypes, without any loss of accuracy in the predicted energy consumption. We experimentally show the effect of this fast cost evaluation method when used in an automated instructionset architecture exploration. In our experiments, we compare three different methods for cost estimation and find that we can accurately predict the energy consumption of proposed architectures while avoiding simulation of the complete system.

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“…For example, [12], [14] use a simulation based technique for evaluating the performance of TTA-based ASIPs. In their approach, they store the simulationtrace in a database.…”

Section: Methodsmentioning

confidence: 99%

“…Previous research (e.g. [12]- [15]) has shown that this results in fast and reasonably accurate (e.g. less than 10% error for energy [13]) cost estimations.…”

Section: Introductionmentioning

confidence: 94%

See 1 more Smart Citation

An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors

Jordans

Corvino

Jóźwiak

et al. 2013

2013 Euromicro Conference on Digital System Design

View full text Add to dashboard Cite

show abstract

“…In particular, we use design space exploration, seeded with synthesized C code and a minimal architecture. During the exploration process, the explorer repeatedly attempts to extend the processor with various resources, or removes unused or rarely used resources and evaluates the speed of application on such a processor as well as estimates the energy needed [17]. After the exploration process completes, the designer is able to select the architecture based on restrictions given on speed, area or energy.…”

Section: B Automated Application-specific Instruction Set Extension mentioning

confidence: 99%

An integrated ASIP design flow for digital signal processing applications

Guzma

Bhattacharyya

Kellomäki

et al. 2008

2008 First International Symposium on Applied Sciences on Biomedical and Communication Technologies

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Application specific instruction set processors (ASIP) allow designers to optimize the architecture of an embedded processor to meet the specific demands of a particular application. A complementary form of customization is provided by domain-specific models of computation (MoCs), which can expose the high level structure of applications that is useful for various kinds of optimizing design transformations. One such MoC is Synchronous Dataflow (SDF), which is used increasingly in the design and implementation of signal processing applications. In this paper, we develop an integration of SDF-and ASIP-oriented design flows, and use this integrated design flow to explore trade-offs in the space of hardware/software implementations. We also explore an approach to ASIP implementation in terms of "critical" and "non-critical" applications, which allows designers to tune the degree of specialization for a targeted ASIP. Our results show that single ASIP processor tuned for pair of critical applications saves 26% to 50% of area required for implementations of two applications on separate ASIPs and noncritical applications runs on such processor with in worst case 4.5% overhead for our selection of benchmarks.

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“…The exploration algorithm includes or excludes processor resources one by one followed by re-compilation and simulation of the program. The explorer is improved for higher accuracy in [5] but the principle is unchanged. A similar kind of exploration flow is presented also in [6].…”

Section: Introductionmentioning

confidence: 96%

Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations

Salmela

Shen

Bhattacharyya

et al. 2007

2007 IEEE Workshop on Signal Processing Systems

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The implementation of real-time signal processing applications calls for parallelism to avoid unpractical clock frequencies and to lower power consumption. In this paper, a method for exploring the design space of parallel elementary computing resources is proposed. The method can be used to find a suitable set of computing resources for processors applying instruction level parallelism (ILP) or pure hardware designs. The extensive size of the design space is coped with coarse level modeling and evaluation. The method presents the system as a union of multisets of computing resources. This formulation provides a general framework for efficient, multi-objective optimization in terms of relevant cost metrics, including processing latency, area, and power consumption. We demonstrate this framework by developing a multiobjective evolutionary algorithm based on it, and applying this algorithm to a rake receiver application.

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Hardware Cost Estimation for Application-Specific Processor Design

Cited by 11 publications

References 9 publications

An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors

An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors

An integrated ASIP design flow for digital signal processing applications

Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations

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