An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors

Abstract

Design space exploration for ASIP instruction-set design is a very complex problem, involving a large set of architectural choices. Existing methods are usually handcrafted and time-consuming. In this paper, we propose and investigate a rapid method to estimate the energy consumption of candidate architectures for VLIW ASIP processors. The proposed method avoids the time-consuming simulation of the candidate prototypes, without any loss of accuracy in the predicted energy consumption. We experimentally show the effect of this fast cost evaluation method when used in an automated instructionset architecture exploration. In our experiments, we compare three different methods for cost estimation and find that we can accurately predict the energy consumption of proposed architectures while avoiding simulation of the complete system.

BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching

“…Our ASIP architecture exploration method builds upon our efficient method for energy estimation of ASIPs presented in [1]. In our previous research we have shown that accurate estimations of both the energy consumption and the applications cycle count can be obtained using only the assembly listing and the application profile.…”

“…Combining these observations together with our efficient cost estimation technique allowed us to develop an efficient ASIP architecture exploration method which avoiding many simulation runs. In [1], we presented two variations of the cost estimation method: a) a completely static profile-based estimation, which performed a single simulation run and which handled only small changes in the profile, and b), a hybrid estimation which performed a separate simulation for each design but was still a more efficient method than the traditional trace-based cost analysis. However, our previous paper did not present any technique capable of automatically detecting when changes happen to the application profile, making it difficult to use the more efficient profile-based estimation in a reliable way.…”

“…The ASIP architecture exploration process proposed in [1] and [13], evaluates and selects VLIW ASIP architectures according to a predefined template. Exploring the instructionset architecture of VLIW ASIPs is however much more complex than for simple sequential (e.g.…”

“…In our previous research we introduced and investigated a rapid method to estimate the energy consumption of candidate architectures for VLIW ASIP processors [1]. The proposed method avoided the time-consuming simulation of the candidate architecture prototypes, without any loss of accuracy in the predicted energy consumption, as long as changes in the application profile were recognized correctly.…”

“…In section II, we discuss some of the related work on both the simulation and compilation caching. In section III, we briefly re-introduce our architecture exploration techniques and efficient cost estimation methods from [1]. Section IV introduces our new caching methods and section V experimentally evaluates their effectiveness.…”