BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching

Abstract

In this paper we introduce and discuss the Build-Master framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluation of selected designs. In each of the experiments we performed, we were able to reduce the number of required simulations with over 90% and save up to 50% on the required compilation time.

Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm

“…For the experimental evaluation in this paper, the same testcases were used as in [7]. These test-cases are two heartrate detection (ECG) applications (ecg-1 and ecg-2), one AES encryption/decription application (aes), and two image processing kernels (down performing down-sampling, and lpsf performing spatial filtering).…”

“…Firstly, we compare our genetic algorithm to our heuristic exploration methods [4], [7] for both the quality of the final results and the time required for the exploration. Figure 2 shows the final scores obtained using the two heuristic approaches (first-match and best-match) from [4], and compares them against the results obtained by the presented genetic algorithm.…”

“…It uses the BuildMaster framework [7] for this purpose. The BuildMaster framework will then decide if compilation and or simulation is required for this specific instance and will perform the necessary steps to obtain the performance metrics for the proposed candidate.…”

“…This can often reduce the effectiveness of the genetic algorithm and a shortened design-time when compared to a manual design may not always be guaranteed. However, we recently improved upon the current state-of-the-art by introducing compilation and simulation result caching [7] for evaluating the energy and area consumption of proposed VLIW ASIPs. Our caching approach works by efficiently re-using compilation and simulation results when considered architectures sufficiently similar.…”

MIPS Integrated Architectural Memory Design Synthesis for Low Power Embedded Devices

“…Meloni, P., Pomato, S., Raffo, L., Lindwer, M. [7] proposed integrated tool chain design & evaluated the ASIP systems. Jordans, R., Diken, E., Jozwiak, L., Corporaul, H. [8] proposed build master framework. This framework used efficient automated cache compilation and simulation for ASIP.…”