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We report an InP/InGaAs/InP double heterojunction bipolar transistor (DHBT), fabricated using a mesa structure, exhibiting 282 GHz and 400 GHz max . The DHBT employs a 30 nm InGaAs base with carbon doping graded from 8 10 19 /cm 3 to 5 10 19 /cm 3 , an InP collector, and an InGaAs/InAlAs base-collector superlattice grade, with a total 217 nm collector depletion layer thickness. The low base sheet (580 ) and contact ( 10 -m 2 ) resistivities are in part responsible for the high max observed.

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Silicon-on-Lattice Engineered Substrates (SOLES) are SOI substrates with embedded Ge layers that facilitate III-V compound integration for advanced integrated circuits. The new materials integration scheme in SOLES requires the analysis of its thermal stability and diffusion barrier properties. In this study, we report on the successful monolithic integration of CMOS/III-V transistors with a reduced CMOS thermal budget. We further investigated the ultimate thermal budget limits for the SOLES platform. We demonstrated a new SOLES structure incorporating a SiN x interlayer, which adds greater integration flexibility for future circuit applications.

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