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This paper describes integration of an advanced composite high-K gate stack (4nm TaSiO x -2nm InP) in the In 0.7 Ga 0.3 As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (t OXE ) and low gate leakage (J G ) and (ii) effective carrier confinement and high effective carrier velocity (V eff ) in the QW channel. The L G =75nm In 0.7 Ga 0.3 As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750μS/μm and high drive current of 0.49mA/μm at V DS =0.5V.

Time-resolved photoluminescence measurements reveal a minority carrier lifetime of >412 ns at 77 K under low excitation for a long-wavelength infrared InAs/InAs0.72Sb0.28 type-II superlattice (T2SL). This lifetime represents an order-of-magnitude increase in the minority carrier lifetime over previously reported lifetimes in long-wavelength infrared InAs/Ga1−xInxSb T2SLs. The considerably longer lifetime is attributed to a reduction of non-radiative recombination centers with the removal of Ga from the superlattice structure. This lifetime improvement may enable background limited T2SL long-wavelength infrared photodetectors at higher operating temperatures.

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Type II arsenide/antimonide compound semiconductor with highly staggered GaAs 0.35 Sb 0.65 /In 0.7 Ga 0.3 As hetero-junction is used to demonstrate hetero tunnel FET (TFET) with record high drive currents (I ON ) of 190µA/µm and 100µA/µm at V DS =0.75V and 0.3V, respectively (L G =150nm). In x Ga 1-x As (x=0.53, 0.7) homo-junction TFETs and GaAs 0.5 Sb 0.5 /In 0.53 Ga 0.47 As hetero TFET with moderate stagger are also fabricated with the same process flow for benchmarking. Measured and simulated TFET performance is benchmarked with 40nm strained Si MOSFETs for 300mV logic applications. IntroductionInter-band tunnel FETs (TFETs) are promising devices for realizing sub-kT/q steep switching slope (SS). Compared to MOSFET, however, the TFET drive current (I ON ) is considerably low due to the large source side tunneling barrier (E beff ). Bandgap (E g ) engineered III-V hetero-junctions could meet the I ON requirement while achieving sub-kT/q SS and low off-state leakage current (I OFF ) (1). In this work, we experimentally demonstrate GaAs 0.35 Sb 0.65 /In 0.7 Ga 0.3 As highly staggered hetero-junction TFET and show 400% I ON enhancement over corresponding In 0.7 Ga 0.3 As homo-junction TFET. Using calibrated numerical simulations, we further show that MOSFET-like high I ON can be achieved using highly staggered hetero-junction, ultra thin body and low EOT for Vcc=300mV logic applications.

Articles you may be interested inThe structural, morphological, defect properties, and OFF state leakage current mechanism of mixed As-Sb type-II staggered gap GaAs-like and InAs-like interface heterostructure tunnel field effect transistors (TFETs) grown on InP substrates using linearly graded In x Al 1-x As buffer by molecular beam epitaxy are investigated and compared. Symmetric relaxation of >90% and >75% in the two orthogonal h110i directions with minimal lattice tilt was observed for the terminal GaAs 0.35 Sb 0.65 and In 0.7 Ga 0.3 As active layers of GaAs-like and InAs-like interface TFET structures, respectively, indicating that nearly equal numbers of a and b dislocations were formed during the relaxation process. Atomic force microscopy reveals extremely ordered crosshatch morphology and low root mean square roughness of $3.17 nm for the InAs-like interface TFET structure compared to the GaAs-like interface TFET structure of $4.46 nm at the same degree of lattice mismatch with respect to the InP substrates. The GaAs-like interface exhibited higher dislocation density, as observed by cross-sectional transmission electron microscopy, resulting in the elongation of reciprocal lattice point of In 0.7 Ga 0.3 As channel and drain layers in the reciprocal space maps, while the InAs-like interface creates a defect-free interface for the pseudomorphic growth of the In 0.7 Ga 0.3 As channel and drain layers with minimal elongation along the Dx direction. The impact of the structural differences between the two interface types on metamorphic TFET devices was demonstrated by comparing p þ -i-n þ leakage current of identical TFET devices that were fabricated using GaAs-like and InAs-like interface TFET structures. Higher OFF state leakage current dominated by band-to-band tunneling process due to higher degree of defects and dislocations was observed in GaAs-like interface compared to InAs-like interface where type-II staggered band alignment was well maintained. Significantly lower OFF state leakage current dominated by the field enhanced Shockley-Read-Hall generation-recombination process at different temperatures was observed in InAs-like TFET structure. The fixed positive charge at the source/channel heterointerface influences the band lineup substantially with charge density greater than 1 Â 10 12 /cm 2 and the band alignment is converted from staggered gap to broken gap at $6 Â 10 12 /cm 2 . Clearly, InAs-like interface TFET structure exhibited 4Â lower OFF state leakage current, which is attributed primarily to the impact of the layer roughness, defect properties on the carrier recombination rate, suggesting great promise for metamorphic TFET devices for high-performance, and ultra-low power applications. V C 2012 American Institute of Physics.

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