Heterogeneous integration of enhancement mode in<sub>0.7</sub>ga<sub>0.3</sub>as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications

Hudait, Mantu K.; Dewey, G.; Datta, Suman; Fastenau, J. M.; Kavalieros, J.; Liu, W.K.; Lubyshev, D.; Pillarisetty, R.; Rachmady, W.; Radosavljević, M.; Rakshit, Titash; Chau, R.

doi:10.1109/iedm.2007.4419017

Cited by 65 publications

(72 citation statements)

References 3 publications

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“…High-mobility III-V semiconductors, such as InGaAs/InP-and GaSb/ InAs-based materials, are of great interest for digital logic device applications due to their potential to replace Si channel in emerging MOSFETs and their potential for developing innovative device structures like tunnel FETs [2,68]. Both MBE and MOCVD have demonstrated excellent InGaAs QW heterostructures on (001) Si substrates [64,66,69,70], with room-temperature Hall mobilities exceeding 10,000 cm 2 /V . s, matching the best results on native InP substrates.…”

Section: Wafer-scale Hetero-epitaxial Growth Of Iii-v Thin Ilms On Simentioning

confidence: 99%

“…6. Different transistor structures, including QW ield-effect transistors with Schottky gates [69,71], and QW channel MOSFETs with high-k dielectrics [70] and source/drain regrowth [72][73][74][75][76], have been reported. These exploratory transistors demonstrated record-high drive current and extrinsic transconductance at low operation voltages, suggesting potential for high-speed switching applications with reduced power consumption.…”

Section: Wafer-scale Hetero-epitaxial Growth Of Iii-v Thin Ilms On Simentioning

confidence: 99%

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Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Lau

2017

Progress in Crystal Growth and Characterization of Materials

113

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Please note: Changes made as a result of publishing processes such as copy-editing, formatting and page numbers may not be reflected in this version. For the definitive version of this publication, please refer to the published source. You are advised to consult the publisher's version if you wish to cite this paper.This version is being made available in accordance with publisher policies. See http://orca.cf.ac.uk/policies.html for usage policies. Copyright and moral rights for publications made available in ORCA are retained by the copyright holders. U N C O R R E C T E D P R O O F ARTICLE INFO ABSTRACTMonolithic integration of III-V on silicon has been a scientifically appealing concept for decades. Notable progress has recently been made in this research area, fueled by significant interests of the electronics industry in high-mobility channel transistors and the booming development of silicon photonics technology. In this review article, we outline the fundamental roadblocks for the epitaxial growth of highly mismatched III-V materials, including arsenides, phosphides, and antimonides, on (001) oriented silicon substrates. Advances in hetero-epitaxy and selective-area hetero-epitaxy from micro to nano length scales are discussed. Opportunities in emerging electronics and integrated photonics are also presented.

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Section: Wafer-scale Hetero-epitaxial Growth Of Iii-v Thin Ilms On Simentioning

confidence: 99%

Section: Wafer-scale Hetero-epitaxial Growth Of Iii-v Thin Ilms On Simentioning

confidence: 99%

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Lau

2017

Progress in Crystal Growth and Characterization of Materials

113

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“…In order to sustain a better gate capacitance scalability for metal-oxide-semiconductor (MOS) device application, high-k dielectrics have been deposited onto the III-V semiconductor substrates, such as GaAs and InGaAs [2][3][4][5][6][7][8][9][10][11][12].…”

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confidence: 99%

Synchrotron radiation photoemission spectroscopic study of band offsets and interface self-cleaning by atomic layer deposited HfO2 on In0.53Ga0.47As and In0.52Al0.48As

Kobayashi

Chen

Sun

et al. 2008

Applied Physics Letters

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whereas in-situ vacuum annealing removes surface arsenic pile-up. After the atomic layer deposition of HfO 2 , native oxides were considerably reduced compared to that in as-received epi-layers, strongly suggesting the self-clean mechanism. Valence and conduction band offsets are measured to be 3.37±0.1eV, 1.80±0.3eV for In 0.53 Ga 0.47 As and 3.00±0.1eV, 1.47±0.3eV for In 0.52 Al 0.47 As, respectively.

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“…A pFET version has been demonstrated in the Si/Ge material system, Figure 1. For nFETs, the Ge concentration in the channel needs to be lower than the substrate concentration to get the desired conduction band offset: in this case a structure with a Si 1-x Ge x -channel on a Si 1-y Ge y Strain-Relaxed Buffer (SRB) can be imagined (x<y), besides various solutions in the III/V material systems (10)(11)(12). IFQW pFETs show excellent performance and electrostatics (14)(15)(16).…”

Section: Introductionmentioning

confidence: 99%

(Invited) Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors

Eneman¹,

Witters²,

Collaert³

et al. 2012

ECS Trans.

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Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type FinFETs and p-type Si1-xGex-channel pFETs, and relies mainly on TCAD results. It will be shown that on n-FinFETs, tensile stressed Contact Etch-Stop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. Tensile stressed gates are shown to be an effective stressor on gate-first n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. For pFETs with strained Si1-xGex-channels like the Implant-Free Quantum Well (IFQW) FET, it will be shown that elastic relaxation during source/drain recess is an important factor that reduces the effectiveness of Si1 yGey source/drain stressors. For scaled technologies, omitting the source/drain recess altogether and opting for a raised source/drain scheme is preferred. In IFQW pFETs, dependence of the drive current on transistor width is an important concern. It will be shown that a Si1 yGey source/drain reduces the layout dependence of IFQW FETs, an effect that is enhanced further when combined with a gate-last integration scheme.

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Heterogeneous integration of enhancement mode in_0.7ga_0.3as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications

Cited by 65 publications

References 3 publications

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Synchrotron radiation photoemission spectroscopic study of band offsets and interface self-cleaning by atomic layer deposited HfO2 on In0.53Ga0.47As and In0.52Al0.48As

(Invited) Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors

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Heterogeneous integration of enhancement mode in0.7ga0.3as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications

Cited by 65 publications

References 3 publications

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Synchrotron radiation photoemission spectroscopic study of band offsets and interface self-cleaning by atomic layer deposited HfO2 on In0.53Ga0.47As and In0.52Al0.48As

(Invited) Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors

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Heterogeneous integration of enhancement mode in_0.7ga_0.3as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications