Articles you may be interested inThe structural, morphological, defect properties, and OFF state leakage current mechanism of mixed As-Sb type-II staggered gap GaAs-like and InAs-like interface heterostructure tunnel field effect transistors (TFETs) grown on InP substrates using linearly graded In x Al 1-x As buffer by molecular beam epitaxy are investigated and compared. Symmetric relaxation of >90% and >75% in the two orthogonal h110i directions with minimal lattice tilt was observed for the terminal GaAs 0.35 Sb 0.65 and In 0.7 Ga 0.3 As active layers of GaAs-like and InAs-like interface TFET structures, respectively, indicating that nearly equal numbers of a and b dislocations were formed during the relaxation process. Atomic force microscopy reveals extremely ordered crosshatch morphology and low root mean square roughness of $3.17 nm for the InAs-like interface TFET structure compared to the GaAs-like interface TFET structure of $4.46 nm at the same degree of lattice mismatch with respect to the InP substrates. The GaAs-like interface exhibited higher dislocation density, as observed by cross-sectional transmission electron microscopy, resulting in the elongation of reciprocal lattice point of In 0.7 Ga 0.3 As channel and drain layers in the reciprocal space maps, while the InAs-like interface creates a defect-free interface for the pseudomorphic growth of the In 0.7 Ga 0.3 As channel and drain layers with minimal elongation along the Dx direction. The impact of the structural differences between the two interface types on metamorphic TFET devices was demonstrated by comparing p þ -i-n þ leakage current of identical TFET devices that were fabricated using GaAs-like and InAs-like interface TFET structures. Higher OFF state leakage current dominated by band-to-band tunneling process due to higher degree of defects and dislocations was observed in GaAs-like interface compared to InAs-like interface where type-II staggered band alignment was well maintained. Significantly lower OFF state leakage current dominated by the field enhanced Shockley-Read-Hall generation-recombination process at different temperatures was observed in InAs-like TFET structure. The fixed positive charge at the source/channel heterointerface influences the band lineup substantially with charge density greater than 1 Â 10 12 /cm 2 and the band alignment is converted from staggered gap to broken gap at $6 Â 10 12 /cm 2 . Clearly, InAs-like interface TFET structure exhibited 4Â lower OFF state leakage current, which is attributed primarily to the impact of the layer roughness, defect properties on the carrier recombination rate, suggesting great promise for metamorphic TFET devices for high-performance, and ultra-low power applications. V C 2012 American Institute of Physics.

High-quality epitaxial Ge layers for GaAs/Ge/GaAs heterostructures were grown in situ in an arsenic-free environment on (100) off-oriented GaAs substrates using two separate molecular beam epitaxy (MBE) chambers, connected via vacuum transfer chamber. The structural, morphological, and band offset properties of these heterostructures are investigated. Reflection high energy electron diffraction studies exhibited (2 Â 2) Ge surface reconstruction after the growth at 450 C and also revealed a smooth surface for the growth of GaAs on Ge. High-resolution triple crystal x-ray rocking curve demonstrated high-quality Ge epilayer as well as GaAs/Ge/(001)GaAs heterostructures by observing Pendell€ osung oscillations and that the Ge epilayer is pseudomorphic. Atomic force microscopy reveals smooth and uniform morphology with surface roughness of $0.45 nm and room temperature photoluminescence spectroscopy exhibited direct bandgap emission at 1583 nm. Dynamic secondary ion mass spectrometry depth profiles of Ga, As, and Ge display a low value of Ga, As, and Ge intermixing at the Ge/GaAs interface and a transition between Ge/GaAs of less than 15 nm. The valence band offset at the upper GaAs/Ge-(2 Â 2) and bottom Ge/(001)GaAs-(2 Â 4) heterointerface of GaAs/Ge/GaAs double heterostructure is about 0.20 eV and 0.40 eV, respectively. Thus, the high-quality heterointerface and band offset for carrier confinement in MBE grown GaAs/Ge/GaAs heterostructures offer a promising candidate for Ge-based p-channel high-hole mobility quantum well field effect transistors. V

Articles you may be interested inTunneling field-effect transistor with Ge/In0.53Ga0.47As heterostructure as tunneling junction J. Appl. Phys. 113, 094502 (2013) The compositional dependence of effective tunneling barrier height (E beff ) and defect assisted band alignment transition from staggered gap to broken gap in GaAsSb/InGaAs n-channel tunnel field effect transistor (TFET) structures were demonstrated by x-ray photoelectron spectroscopy (XPS). High-resolution x-ray diffraction measurements revealed that the active layers are internally lattice matched. The evolution of defect properties was evaluated using cross-sectional transmission electron microscopy. The defect density at the source/channel heterointerface was controlled by changing the interface properties during growth. By increasing indium (In) and antimony (Sb) alloy compositions from 65% to 70% in In x Ga 1Àx As and 60% to 65% in GaAs 1Ày Sb y layers, the E beff was reduced from 0.30 eV to 0.21 eV, respectively, with the low defect density at the source/channel heterointerface. The transfer characteristics of the fabricated TFET device with an E beff of 0.21 eV show 2Â improvement in ON-state current compared to the device with E beff of 0.30 eV. On contrary, the value of E beff was decreased from 0.21 eV to À0.03 eV due to the presence of high defect density at the GaAs 0.35 Sb 0.65 /In 0.7 Ga 0.3 As heterointerface. As a result, the band alignment was converted from staggered gap to broken gap, which leads to 4 orders of magnitude increase in OFF-state leakage current. Therefore, a high quality source/channel interface with a properly selected E beff and well maintained low defect density is necessary to obtain both high ON-state current and low OFF-state leakage in a mixed As/Sb TFET structure for high-performance and lower-power logic applications. V C 2012 American Institute of Physics. [http://dx