Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration

Yang, Nancy Y. C.; Bulsara, Mayank T.; Fitzgerald, Eugene A.; Liu, W.K.; Lubyshev, D.; Fastenau, J. M.; Wu, Ying; Urteaga, M.; Ha, Wonill; Bergman, J.; Brar, B.; Drazekd, C.; Daval, N.; Benaissa, L.; Augendre, E.; Hoke, W. E.; LaRoche, J. R.; Herrick, K.J.; Kazior, T.E.

doi:10.1109/soi.2009.5318745

Cited by 3 publications

(8 citation statements)

References 3 publications

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“…For Structure A, Ge concentrations after annealing according to the thermal budget of the CMOS process utilized for the integrated InP HBT previously reported by Liu et al and Yang et al 4,5 is shown. Though some Ge diffusion through the BOX does occur, the modified thermal budget successfully curtails the extent of this diffusion and eliminates high Ge accumulation levels at the Si/SiO 2 interface.…”

Section: Ge-based Solesmentioning

confidence: 96%

“…2, top. 5 At 940 ± 5 • C, Ge melting, agglomeration and film delamination can clearly be seen. For Ge-OI SOLES wafers annealed at 920 ± 5…”

Section: Ge-based Solesmentioning

confidence: 97%

“…2, top. 5 At 940 ± 5 • C, Ge melting, agglomeration and film delamination can clearly be seen. For Ge-OI SOLES wafers annealed at 920 ± 5 • C, neither TEM nor Nomarski reveals any structural change in the buried Ge layer.…”

Section: Ge-based Solesmentioning

confidence: 97%

“…Allowable thermal budgets for device processing were determined for the Ge SOLES samples. The wafers were cleaved into pieces and annealed in a tube furnace in N 2 ambient for 8.5 hours at temperatures up to 940 ± 5 • C. This duration was chosen to be consistent with a safe thermal budget devised for the previous implementation of monolithically integrated InP HBT and Si CMOS, reported by Yang et al 5 Plan-view optical microscopy (Nomarski) and cross sectional transmission electron microscopy (TEM) were used to confirm structural changes in the wafers after annealing whereas secondary ion mass spectroscopy (SIMS) was performed in order to determine Ge diffusion profiles in the substrates. TEM samples were made by cleaving the wafers into small pieces, manually polishing with silicon carbide lapping film of successively finer grit size, followed by ion milling at a glancing angle of 15 o .…”

Section: Ge-based Solesmentioning

confidence: 99%

“…Though some Ge diffusion through the BOX does occur, the modified thermal budget successfully curtails the extent of this diffusion and eliminates high Ge accumulation levels at the Si/SiO 2 interface. 5 For Structures B, C and D, the Ge profile in the as-fabricated wafers are shown in Fig. 3, together with the Ge diffusion profile after 805 ± 5 • C, 855 ± 5 • C and 920 ± 5 • C. The location of Si/SiO 2 and SiO 2 /SiO 2 interfaces can be easily identified by Ge spikes.…”

Section: Ge-based Solesmentioning

confidence: 99%

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Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates

Pacella

Bulsara

Drazek

et al. 2015

ECS J. Solid State Sci. Technol.

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The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device template layer which serves as a seed surface for epitaxial growth of III-V devices. In this work, different approaches for fabricating SOLES wafers comprised of Ge and InP template layers are characterized and InP-based SOLES structures are demonstrated for the first time. Ge-based SOLES are robust for long durations at temperatures up to 915 • C and Ge diffusion can be controlled by engineering the oxide isolation layers adjacent to the Ge. InP SOLES structures alleviate lattice and thermal expansion mismatches between the template layer and subsequent device layers. Although allowable processing temperatures for these wafers had been expected to be higher due to the higher melting temperature of InP, high indium diffusion through the SiO 2 and InP melting actually lead to lower thermal stability. This research elucidates approaches to enhance the process flexibility and wafer integrity of Ge-based and InP-based SOLES. Monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal-oxide semiconductor (CMOS) enables advanced circuits with increased performance and functionality and promotes system-level miniaturization. The Silicon on Lattice Engineered Substrate (SOLES) platform is a Si wafer with embedded III-V template layer that has been developed for III-V/Si integration and is illustrated in Fig. 1. 1,2 A silicon-on-insulator (SOI) layer on top provides the high quality substrate necessary for CMOS device processing whereas the III-V template acts as a seed layer for epitaxial III-V device growth. This III-V template layer is accessed by etching windows through the top Si and buried insulator layers. The SOLES substrate structure is designed to add functionality to a CMOS platform while maintaining compatibility with Si processing infrastructure. Exposure to the III-V template layer is avoided until the CMOS process sequence is complete and the III-V device epitaxy and processing can be treated in a similar manner to backend metal processing.

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Section: Ge-based Solesmentioning

confidence: 96%

“…2, top. 5 At 940 ± 5 • C, Ge melting, agglomeration and film delamination can clearly be seen. For Ge-OI SOLES wafers annealed at 920 ± 5…”

Section: Ge-based Solesmentioning

confidence: 97%

Section: Ge-based Solesmentioning

confidence: 97%

Section: Ge-based Solesmentioning

confidence: 99%

Section: Ge-based Solesmentioning

confidence: 99%

See 3 more Smart Citations

Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates

Pacella

Bulsara

Drazek

et al. 2015

ECS J. Solid State Sci. Technol.

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Si CMOS Contacts to III-V Materials for Monolithic Integration of III-V and Si Devices

2011

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Si CMOS-based contact metallurgies to III-V compounds will allow parallel interconnection of Si CMOS and III-V devices and promote monolithic integration. In this study, we report the use of nickel silicides to contact n++ GaAs encapsulated with n++ Si. The structure and electrical properties of contacts with varying reaction depths is correlated. Specific contact resistivities lower than 5e-7 ohm-cm 2 are measured on NiSi/Si/GaAs structures.

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Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials

Pacella

Mukherjee

Bulsara

et al. 2013

ECS J. Solid State Sci. Technol.

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Silicon (Si)-encapsulated III-V compound (III-V) device layers enable Si-complementary metal-oxide semiconductor (CMOS) friendly ohmic contact formation to III-V compound devices, allowing for the ultimate seamless planar integration of III-V and Si CMOS devices in a common fabrication infrastructure. A method of making ohmic contacts to buried III-V films using silicide metallurgies has been established. NiSi/Si/III-V dual heterojunction contact structures are found to be optimal for integration. These structures allow contact resistivities to be controlled by Si/III-V interfaces and eliminate interactions between the buried III-V device and metal layers. Using a modified transmission line method (TLM) test structure fabricated using standard CMOS processing techniques, the specific contact resistivities of Si/GaAs and Si/In x Ga 1-x As interfaces are extracted. The relationship between specific contact resistivity and heterojuntion barrier width is considered. Among the structures tested in this work, p-type Si/GaAs and n-type Si/In x Ga 1-x As yielded the lowest contact resistivities. Using the p-type Si/GaAs interface, a GaAs/Al x Ga 1-x As laser with NiSi top contact is demonstrated, confirming the feasibility of NiSi/Si/III-V contact structures for III-V devices. Integration of III-V compound (III-V) semiconductors with Si complementary metal-oxide semiconductor (CMOS) has been an area of great interest because of the circuit performance enhancement that can be gained by placing Si and III-V devices in close spatial proximity. The Silicon-on-Lattice-Engineered Substrate (SOLES) platform enables this integration monolithically. The SOLES wafer is a silicon wafer with an embedded template suitable for epitaxial III-V device growth.1-3 CMOS devices are fabricated on the surface silicon and III-V devices are built on the template layer in windows. In collaboration with other groups, we have successfully demonstrated differential amplifiers with InP heterojunction bipolar transistors (HBT) and Si CMOS devices on SOLES substrates. 4 In this previous work, Si and III-V contact metallization steps were performed separately in traditional CMOS and III-V infrastructure, respectively. We envision parallel metallization of the CMOS and III-V devices using common CMOS infrastructure, in a manner consistent with Si processing, as a final step toward ultimate monolithic integration.A few key requirements must be considered in choosing the optimal contact structure. Contacting the III-V films through a Si encapsulation layer which fully embeds the III-V device and minimizes exposure of III-V materials to the CMOS sequence will cause the least disruption to CMOS processes. This Si may be grown in an epitaxial step that is integrated with III-V device growth, streamlining the growth process.Using CMOS-friendly metals and processing steps which parallel those currently found in CMOS processing will also ease the integration. This metal must have a thermal budget of formation that is low to minimize effects on the III-V devic...

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Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration

Cited by 3 publications

References 3 publications

Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates

Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates

Si CMOS Contacts to III-V Materials for Monolithic Integration of III-V and Si Devices

Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials

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