Coherent Heat Flow Typically, heat in solids is transported incoherently because phonons scatter at interfaces and defects. Luckyanova et al. (p. 936 ) grew super-lattice films made from one to nine repeats of layers of GaAs and AlAs, each 12-nm thick. Thermal conductivity through this sandwich structure increased linearly with the number of superlattice repeats, which is consistent with theoretical simulations of coherent heat transport.

This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the literature on short-channel device performance and process integration of strained Si. The review concludes with a global summary of the mobility enhancements available in the SiGe materials system and a discussion of implications for future technology generations.

Epitaxy-the growth of a crystalline material on a substrate-is crucial for the semiconductor industry, but is often limited by the need for lattice matching between the two material systems. This strict requirement is relaxed for van der Waals epitaxy, in which epitaxy on layered or two-dimensional (2D) materials is mediated by weak van der Waals interactions, and which also allows facile layer release from 2D surfaces. It has been thought that 2D materials are the only seed layers for van der Waals epitaxy. However, the substrates below 2D materials may still interact with the layers grown during epitaxy (epilayers), as in the case of the so-called wetting transparency documented for graphene. Here we show that the weak van der Waals potential of graphene cannot completely screen the stronger potential field of many substrates, which enables epitaxial growth to occur despite its presence. We use density functional theory calculations to establish that adatoms will experience remote epitaxial registry with a substrate through a substrate-epilayer gap of up to nine ångströms; this gap can accommodate a monolayer of graphene. We confirm the predictions with homoepitaxial growth of GaAs(001) on GaAs(001) substrates through monolayer graphene, and show that the approach is also applicable to InP and GaP. The grown single-crystalline films are rapidly released from the graphene-coated substrate and perform as well as conventionally prepared films when incorporated in light-emitting devices. This technique enables any type of semiconductor film to be copied from underlying substrates through 2D materials, and then the resultant epilayer to be rapidly released and transferred to a substrate of interest. This process is particularly attractive in the context of non-silicon electronics and photonics, where the ability to re-use the graphene-coated substrates allows savings on the high cost of non-silicon substrates.

A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge substrates.

We have grown compositionally graded GexSi1−x layers on Si at 900 °C with both molecular beam epitaxy and rapid thermal chemical vapor deposition techniques. Triple-crystal x-ray diffraction reveals that for 0.10<x<0.53, the layers are totally relaxed. GexSi1−x cap layers grown on these graded layers are threading-dislocation-free when examined with conventional plan-view and cross-sectional transmission electron microscopy. Electron beam induced current images were used to count the low threading dislocation densities, which were 4×105±5×104 cm−2 and 3×106±2×106 cm−2 Eq. 2×106 cm−2 for x=0.23 and x=0.50, respectively. Photoluminescence spectra from the cap layers are identical to photoluminescence from bulk GexSi1−x.

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Strained Si n -channel metal-oxide-semiconductor field-effect transistors formed on very thin SiGe relaxed layer fabricated by ion implantation technique Appl. Phys. Lett. 90, 202101 (2007); 10.1063/1.2739324 Asymmetric strain relaxation in patterned SiGe layers: A means to enhance carrier mobilities in Si cap layers Appl. Phys. Lett. 90, 032108 (2007); 10.1063/1.2431702High-quality strain-relaxed SiGe alloy grown on implanted silicon-on-insulator substrate Surface channel strained Si metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒ are a leading contender for future high performance complementary metal-oxide-semiconductor ͑CMOS͒ applications. The carrier mobility enhancement of these devices is studied as a function of channel strain, and the saturation behavior for n-and p-channel devices is compared. Carrier mobility enhancements of up to 1.8 and 1.6 are achieved for n-and p-channel devices, respectively. The process stability of strained Si MOSFETs is also studied, and carrier mobility enhancement is shown to be robust after well implantation and virtual substrate planarization steps. The effects of high-temperature implant activation anneals are also studied. While no misfit dislocation introduction or strain relaxation is observed in these devices, increased interface state densities or alloy scattering due to Ge interdiffusion are shown to decrease mobility enhancements. Channel thickness effects are also examined for strained Si n-MOSFETs. Loss of carrier confinement severely limits the mobility of devices with the thinnest channels. Overall, surface channel strained Si MOSFETs are found to exhibit large carrier mobility enhancements over coprocessed bulk Si devices. This, combined with the high process stability exhibited by these devices, makes them superb candidates for future CMOS applications.

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