A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge substrates.
Strained Si n -channel metal-oxide-semiconductor field-effect transistors formed on very thin SiGe relaxed layer fabricated by ion implantation technique Appl. Phys. Lett. 90, 202101 (2007); 10.1063/1.2739324 Asymmetric strain relaxation in patterned SiGe layers: A means to enhance carrier mobilities in Si cap layers Appl. Phys. Lett. 90, 032108 (2007); 10.1063/1.2431702High-quality strain-relaxed SiGe alloy grown on implanted silicon-on-insulator substrate Surface channel strained Si metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒ are a leading contender for future high performance complementary metal-oxide-semiconductor ͑CMOS͒ applications. The carrier mobility enhancement of these devices is studied as a function of channel strain, and the saturation behavior for n-and p-channel devices is compared. Carrier mobility enhancements of up to 1.8 and 1.6 are achieved for n-and p-channel devices, respectively. The process stability of strained Si MOSFETs is also studied, and carrier mobility enhancement is shown to be robust after well implantation and virtual substrate planarization steps. The effects of high-temperature implant activation anneals are also studied. While no misfit dislocation introduction or strain relaxation is observed in these devices, increased interface state densities or alloy scattering due to Ge interdiffusion are shown to decrease mobility enhancements. Channel thickness effects are also examined for strained Si n-MOSFETs. Loss of carrier confinement severely limits the mobility of devices with the thinnest channels. Overall, surface channel strained Si MOSFETs are found to exhibit large carrier mobility enhancements over coprocessed bulk Si devices. This, combined with the high process stability exhibited by these devices, makes them superb candidates for future CMOS applications.
We show that pure Ge grown selectively on SiO2/Si substrates in 100 nm holes is highly perfect at the top surface compared to conventional Ge lattice-mismatched growth on planar Si substrates. This result is achieved through a combination of interferometric lithography SiO2/Si substrate patterning and ultrahigh vacuum chemical vapor deposition Ge selective epitaxial growth. This “epitaxial necking,” in which threading dislocations are blocked at oxide sidewalls, shows promise for dislocation filtering and the fabrication of low-defect density Ge on Si. Defects at the Ge film surface only arise at the merging of epitaxial lateral overgrowth fronts from neighboring holes. These results confirm that epitaxial necking can be used to reduce threading dislocation density in lattice-mismatched systems.
We have fabricated strained Ge channel ptype metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Si 0.3 Ge 0.7 virtual substrates. The poor interface between silicon dioxide (SiO 2) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400ºC. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly 8 times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm 2 /V-s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement mode MOSFET with buried channellike transport characteristics.
The integration of Ge photodetectors on silicon substrates is advantageous for various Si-based optoelectronics applications. We have fabricated integrated Ge photodiodes on a graded optimized relaxed SiGe buffer on Si. The dark current in the Ge mesa diodes, Js=0.15 mA/cm2, is close to the theoretical reverse saturation current and is a record low for Ge diodes integrated on Si substrates. Capacitance measurements indicate that the detectors are capable of operating at high frequencies (2.35 GHz). The photodiodes exhibit an external quantum efficiency of η=12.6% at λ=1.3 μm laser excitation in the photodiodes. The improvement in Ge materials quality and photodiode performance is derived from an optimized relaxed buffer process that includes a chemical mechanical polishing step within the dislocated epitaxial structure.
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