Production of next generation InP-HBT epiwafers by MBE

Lubyshev, D.; Malis, Oana; Teker, Kasif; Wu, Ying; Fastenau, J. M.; Fang, X. M.; Doss, Christopher; Cornfeld, A.; Liu, W.K.

doi:10.1109/iciprm.2003.1205396

Cited by 4 publications

(4 citation statements)

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“…The full width at half maximum (FWHM) of the corresponding rocking curve around (004) InGaAs reflection is ≈1370 arcsec, which corresponds to a threading dislocation density (TDD) of about 3 × 10 9 cm 2 according to Ayer's model. 20) The best values reported so far for InGaAs virtual substrates are as low as 10 8 cm −2 , 21) comparable to values reported for layers grown by the aspect ratio trapping (ART) method. 22) All these substrate characterizations indicate that the transfer layer process do not damage the structural quality of the III-V active layer.…”

Section: Resultssupporting

confidence: 69%

300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart Cut™ technology

Widiez

Sollier

Baron

et al. 2016

Jpn. J. Appl. Phys.

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This paper reports the first demonstration of 300 mm In0.53Ga0.47As-on-insulator (InGaAs-OI) substrates. The use of direct wafer bonding and the Smart Cut™ technology lead to the transfer of high quality InGaAs layer on large Si wafer size (300 mm) at low effective cost, taking into account the reclaim of the III–V on Si donor substrate. The optimization of the three key building blocks of this technology is detailed. (1) The III–V epitaxial growth on 300 mm Si wafers has been optimized to decrease the defect density. (2) For the first time, hydrogen-induced thermal splitting is made inside the indium phosphide (InP) epitaxial layer and a wide implantation condition ranges is observed on the contrary to bulk InP. (3) Finally a specific direct wafer bonding with alumina oxide has been chosen to avoid outgas diffusion at the alumina oxide/III–V compound interface.

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Section: Resultssupporting

confidence: 69%

300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart Cut™ technology

Widiez

Sollier

Baron

et al. 2016

Jpn. J. Appl. Phys.

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“…Unfortunately, these techniques exhibit several deficiencies, such as poor thermal conductivity in thick layers ͑Ͼ1 m͒, have resulted in significant material degradation through the presence of threading dislocations. 9 Recently, a special growth technique involving 90°inter-facial misfit ͑IMF͒ dislocations formed using the III-Sb material systems has been demonstrated. 10,11 In contrast to other growth modes, this approach allows rapid and unencumbered strain relief at the heteroepitaxial interface through the formation of a two dimensional ͑2D͒, periodic, IMF array comprised of pure edge, 90°dislocations along both ͓110͔ and ͓110͔ directions.…”

Section: Introductionmentioning

confidence: 99%

Interfacial misfit array formation for GaSb growth on GaAs

Huang

Balakrishnan

Huffaker

2009

Journal of Applied Physics

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The manuscript reports that the initial strain relaxation of highly mismatched GaSb layers grown on GaAs (001) is governed by the two-dimensional (2D), periodic interfacial misfit (IMF) dislocation array growth mode. Under optimized growth conditions, only pure 90° dislocations are generated along both [110] and [11¯0] directions that are located at GaSb/GaAs interface, which leads to very low threading dislocation density propagated along the growth direction. The long-range uniformity and subsequent strain relaxation of the 2D and periodic IMF array are demonstrated via transmission electron microscopy and scanning transmission electron microscopy images at GaSb/GaAs interface.

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“…Ge(001) layers can also be used in conjunction with advanced gate dielectrics such as HfO 2 for the formation of bulk Ge (5) or Ge-On-Insulator (GeOI) (6)(7)(8) -based Metal Oxide Semiconductor Field Effect transistors (MOSFETs) with good hole mobilities. Finally, due to their small lattice mismatch with GaAs (a Ge = 5.65785 Å a GaAs = 5.6533 Å) and similar thermal expansion coefficients, Ge(001) layers can be used as templates for the growth of GaAs-based heterostructures such as diodes and solar cells (9), laser diodes (10), high electron mobility and heterojunction bipolar transistors (11) etc.…”

Section: Introductionmentioning

confidence: 99%

Epitaxial Growth of Ge Thick Layers on Nominal and 6oC off Si(001); Ge Surface Passivation by Si

2008

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In the first part of this paper, we have quantified the surface roughness, the degree of strain relaxation and the defect density in thick Ge layers grown using a low temperature / high temperature approach on nominal and 6°off (towards one of the <110> directions) Si(001) substrates. In the second part, we have succinctly described the Si passivation process we use on Ge prior to gate stack formation in order to obtain high performance p-type metal oxide semiconductor field effect transistors.

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Production of next generation InP-HBT epiwafers by MBE

Cited by 4 publications

References 0 publications

300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart Cut™ technology

300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart Cut™ technology

Interfacial misfit array formation for GaSb growth on GaAs

Epitaxial Growth of Ge Thick Layers on Nominal and 6oC off Si(001); Ge Surface Passivation by Si

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