This paper presents experimental evidence that silicon solar cells can achieve >750 mV open circuit voltage at 1 Sun illumination providing very good surface passivation is present. 753 mV local open circuit voltage was measured on a 50 μm thick non-metalized silicon heterojunction solar cell. The paper also considers a recombination model at open circuit based on the recent Auger and radiative recombination parameterization and the measured surface saturation current density. The loss mechanisms at open circuit and several practical pathways to achieve >760 mV open circuit voltage in silicon heterojunction solar cells are discussed.

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The mathematical dependence of bandgap-voltage offset on Auger and radiative recombination is derived. To study the recombination near the intrinsic limit, we manufacture thin silicon heterojunction test structures designed to minimize surface recombination, and to measure voltages and effective lifetimes near the Auger and radiative limit. Open-circuit voltages over 760 mV were measured on 50-μm-thick structures, leading to bandgap-voltage offsets at open-circuit down to 0.35 V. The Auger and radiative recombination represents over 90% of the recombination at open-circuit. This dominance also holds at the maximum power point, giving pseudo-fill factors of 86%. We demonstrate the potential of thin silicon devices to reach high voltages, and bandgap-voltage offsets in line with the best reported for direct bandgap materials such as gallium indium phosphide and gallium arsenide.

A method of reducing optical losses in the transparent conductive oxides (TCO) used in silicon heterojunction solar cells without compromising with series resistance is described. In the method the thickness of a TCO is reduced two-three times and a hydrogenated dielectric is deposited on top to form a double layer antireflection coating. The conductivity of a thin TCO is increased due to the effect of hydrogen treatment supplied from the capping dielectric during the post deposition annealing. The optimized cells with ITO/SiO x :H stacks achieved more than 41 mA/cm 2 generation current on 120-micron-thick wafers while having approximately 100 Ohm/square sheet resistance. The paper also considers integration of ITO/SiO x :H stacks with Cu plating and using ITO/SiN x /SiO x triple layer antireflection coatings.

High quality surface passivation (Seff < 5 cm/s) was achieved on polished float zone and textured p- and n-type solar grade Czochralski silicon substrates by externally injecting and storing positive or negative charges (>±8 × 1012 cm−2) into a dual layer stack of Plasma Enhanced Chemical Vapor Deposition (PECVD) Silicon Nitride (SiNx)/PECVD Silicon Oxide (SiO2) films using a corona charging tool. We demonstrate long term stability and uniform charge distribution in the SiNx film by manipulating the charge on K center defects while negating the requirement of a high temperature thermal oxide step.

The passivation quality of an a-Si/SiO2/SiNx (aSON) stack deposited by conventional PECVD at <250 °C with and without additional corona charging of SiNx is presented. <2 fA/cm2 surface dark saturation current density and <1 cm/s effective surface recombination velocity were demonstrated on both planar and textured n-type Czochralski (CZ) substrates. It was shown that very good passivation can be achieved using <5 nm a-Si layers to provide low parasitic absorption. We also report effective minority carrier lifetimes >60 ms on 5000 Ω-cm and 20.9 ms on 1.7 Ω-cm mirror polished float zone (FZ) material passivated with aSON stacks.

Silicon heterojunction solar cells have demonstrated high efficiencies through excellent surface passivation. However, the use of amorphous silicon (a-Si) in the structure raises the question of long term stability as a-Si solar cells suffer degradation due to the Staebler-Wronski effect. The stability of a-Si in terms of its ability to passivate silicon wafers is evaluated by measuring the minority carrier lifetime and it is found to be unstable over time. The instability is most evident in thin, -10 nm, intrinsic a-Si only layers where lifetime falls from over 1ms immediately after annealing, to 300JJs one month later. The change in lifetime occurs even in the dark at room temperature with the largest fall in the first few days after deposition. The lifetime can be recovered close to its initial level by annealing the sample in air, indicating that the lifetime change is not due to a simple oxidation of the outer layer of a-Si. However, device measurements where an intrinsic/doped a-Si structure is used for the emitter and contact show no change in open circuit voltage or fill factor after one year. The changes in the passivation during processing has important implications for the sequence of device fabrication, the use of lifetime testing as a diagnostic tool and the passivation of all back contact devices.

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