The escalating cost for next generation lithography (NGL) tools is driven in part by the need for complex sources and optics. The cost for a single NGL tool could exceed $50M in the next few years, a prohibitive number for many companies. As a result, several researchers are looking at low cost alternative methods for printing sub-100 nm features. In the mid-1990’s, several research groups started investigating different methods for imprinting small features. Many of these methods, although very effective at printing small features across an entire wafer, are limited in their ability to do precise overlay. In 1999, Colburn et al. [Proc. SPIE 379 (1999)] discovered that imprinting could be done at low pressures and at room temperatures by using low viscosity UV curable monomers. The technology is typically referred to as step and flash imprint lithography. The use of a quartz template enabled the photocuring process to occur and also opened up the potential for optical alignment of the wafer and template. This article traces the development of nanoimprint lithography and addresses the issues that must be solved if this type of technology is to be applied to high-density silicon integrated circuitry.

This paper presents experimental evidence that silicon solar cells can achieve >750 mV open circuit voltage at 1 Sun illumination providing very good surface passivation is present. 753 mV local open circuit voltage was measured on a 50 μm thick non-metalized silicon heterojunction solar cell. The paper also considers a recombination model at open circuit based on the recent Auger and radiative recombination parameterization and the measured surface saturation current density. The loss mechanisms at open circuit and several practical pathways to achieve >760 mV open circuit voltage in silicon heterojunction solar cells are discussed.

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A method of reducing optical losses in the transparent conductive oxides (TCO) used in silicon heterojunction solar cells without compromising with series resistance is described. In the method the thickness of a TCO is reduced two-three times and a hydrogenated dielectric is deposited on top to form a double layer antireflection coating. The conductivity of a thin TCO is increased due to the effect of hydrogen treatment supplied from the capping dielectric during the post deposition annealing. The optimized cells with ITO/SiO x :H stacks achieved more than 41 mA/cm 2 generation current on 120-micron-thick wafers while having approximately 100 Ohm/square sheet resistance. The paper also considers integration of ITO/SiO x :H stacks with Cu plating and using ITO/SiN x /SiO x triple layer antireflection coatings.

High quality surface passivation (Seff < 5 cm/s) was achieved on polished float zone and textured p- and n-type solar grade Czochralski silicon substrates by externally injecting and storing positive or negative charges (>±8 × 1012 cm−2) into a dual layer stack of Plasma Enhanced Chemical Vapor Deposition (PECVD) Silicon Nitride (SiNx)/PECVD Silicon Oxide (SiO2) films using a corona charging tool. We demonstrate long term stability and uniform charge distribution in the SiNx film by manipulating the charge on K center defects while negating the requirement of a high temperature thermal oxide step.

A multiple-step deep Si etch process involving separate etching and polymerization steps is often employed for fabrication of microelectromechanical systems, microfluidics devices, and other assorted deep structures in Si. An integrated plasma equipment-feature evolution model for this multiple-step deep Si etch process is described in this article. In the two-dimensional plasma equipment model, the etching (SF6/O2) and polymerization [octafluorocyclobutane(c-C4F8)] chemistries are separately simulated assuming steady-state conditions. The outputs of the equipment simulations are combined in a string-based feature profile evolution model to simulate the multiple-step deep Si etch process. In the plasma equipment models, detailed gas phase plasma chemistries including electron impact processes, ion–molecule reactions, and neutral chemistry have been considered for both the etching and polymerization gas mixtures. The plasma–surface interaction mechanisms in the feature profile evolution model are based on qualitative information available in literature and the correlation of modeling results with experimental data. Under the relevant operating conditions, F is assumed to be the primary Si etchant, film deposition in c-C4F8 is due to sticking of C, CF2, and C2F4 under ion bombardment, and the polymer is etched by energetic ions through physical sputtering. It is demonstrated that predictions of the resulting model are in close agreement with experiments. The validated model is used to understand the dynamics of the multiple-step deep Si etch process and how etching characteristics can be controlled using a variety of process parameters. Etching characteristics have been found to be quite sensitive to gas pressure, coil power, bias power, and relative step time during both etching and polymerization processes. The Si etch rate and feature sidewall angle are coupled to each other over a wide range of operating conditions.

Previous work with the mechanical properties of step and flash imprint lithography etch barrier materials has shown bulk volumetric shrinkage trends that could impact imprinted feature dimensions and profile. This article uses mesoscopic and finite element modeling techniques to model the behavior of the etch barrier during polymerization. Model results are then compared to cross section images of template and etch barrier. Volumetric shrinkage is seen to impact imprinted feature profiles largely as a change in feature height.

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