The escalating cost for next generation lithography (NGL) tools is driven in part by the need for complex sources and optics. The cost for a single NGL tool could exceed $50M in the next few years, a prohibitive number for many companies. As a result, several researchers are looking at low cost alternative methods for printing sub-100 nm features. In the mid-1990’s, several research groups started investigating different methods for imprinting small features. Many of these methods, although very effective at printing small features across an entire wafer, are limited in their ability to do precise overlay. In 1999, Colburn et al. [Proc. SPIE 379 (1999)] discovered that imprinting could be done at low pressures and at room temperatures by using low viscosity UV curable monomers. The technology is typically referred to as step and flash imprint lithography. The use of a quartz template enabled the photocuring process to occur and also opened up the potential for optical alignment of the wafer and template. This article traces the development of nanoimprint lithography and addresses the issues that must be solved if this type of technology is to be applied to high-density silicon integrated circuitry.

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The feasibility of using hydrogen silsesquioxane (HSQ) to directly pattern the relief layer of step and flash imprint lithography (SFIL) templates has been successfully demonstrated. HSQ is a spin-coatable oxide, which is capable of high resolution electron-beam lithography. Negative acting and nonchemically amplified, HSQ has moderate electron-beam sensitivity and excellent processing latitude. In this novel approach, 6 ×6 × 0.25 in.3 quartz photomask substrates are coated with a 60 nm indium tin oxide (ITO) charge dissipation layer and directly electron-beam written using a 100 nm film of HSQ. Direct patterning of an oxide relief layer eliminates the problems of critical dimension control associated with both chromium and oxide etches, both required processes of previous template fabrication schemes. Resolution of isolated and semidense lines of 30 nm has been demonstrated on imprinted wafers using this type of template. During this evaluation, a failure of the release layer to provide a durable nonstick surface on ITO was discovered and investigated. This problem was successfully remedied by depositing a 5 nm oxide layer over the patterned ITO/HSQ template.