Flexible electronics has significantly advanced over the last few years, as devices and circuits from nanoscale structures to printed thin films have started to appear. Simultaneously, the demand for high-performance electronics has also increased because flexible and compact integrated circuits are needed to obtain fully flexible electronic systems. It is challenging to obtain flexible and compact integrated circuits as the silicon based CMOS electronics, which is currently the industry standard for high-performance, is planar and the brittle nature of silicon makes bendability difficult. For this reason, the ultra-thin chips from silicon is gaining interest. This review provides an in-depth analysis of various approaches for obtaining ultra-thin chips from rigid silicon wafer. The comprehensive study presented here includes analysis of ultra-thin chips properties such as the electrical, thermal, optical and mechanical properties, stress modelling, and packaging techniques. The underpinning advances in areas such as sensing, computing, data storage, and energy have been discussed along with several emerging applications (e.g., wearable systems, m-Health, smart cities and Internet of Things etc.) they will enable. This paper is targeted to the readers working in the field of integrated circuits on thin and bendable silicon; but it can be of broad interest to everyone working in the field of flexible electronics.
Flexible electronics has huge potential to bring revolution in robotics and prosthetics as well as to bring about the next big evolution in electronics industry. In robotics and related applications, it is expected to revolutionise the way with which machines interact with humans, real-world objects and the environment. For example, the conformable electronic or tactile skin on robot's body, enabled by advances in flexible electronics, will allow safe robotic interaction during physical contact of robot with various objects. Developing a conformable, bendable and stretchable electronic system requires distributing electronics over large non-planar surfaces and movable components. The current research focus in this direction is marked by the use of novel materials or by the smart engineering of the traditional materials to develop new sensors, electronics on substrates that can be wrapped around curved surfaces. Attempts are being made to achieve flexibility/stretchability in e-skin while retaining a reliable operation. This review provides insight into various materials that have been used in the development of flexible electronics primarily for e-skin applications.
This paper presents graphene field-effect transistor (GFET) based pressure sensors for tactile sensing. The sensing device comprises GFET connected with a piezoelectric metal-insulator-metal (MIM) capacitor in an extended gate configuration. The application of pressure on MIM generates a piezo-potential which modulates the channel current of GFET. The fabricated pressure sensor was tested over a range of 23.54-94.18 kPa, and it exhibits a sensitivity of 4.55 Â 10 À3 kPa À1. Further, the low voltage ($100 mV) operation of the presented pressure sensors makes them ideal for wearable electronic applications. V
This paper presents an innovative approach for wafer scale transfer of ultra-thin silicon chips on flexible substrates. The methodology has been demonstrated with various devices (ultrathin chip resistive samples, MOS capacitors and n-channel MOSFETs) on wafers up to 4" diameter. This is supported by extensive electro-mechanical characterization and theoretical analysis, including finite element simulation, to evaluate the effect of bending and the critical breaking radius of curvature. The ultra-thin chips on polyimide did not break until the radius of curvature of 1.437 mm. In the case of MOS capacitors the measured capacitance increases with increase in bending load. The changes in the transfer and output characteristics of ultra-thin MOSFETs closely match with the theoretical model utilizing empirically determined parameters. Overall, the work demonstrates the efficacy of the new methodology presented here for wafer scale transfer of ultra-thin chips on flexible substrates. The presented research will be useful for obtaining high performance and compact circuits needed in many futuristic flexible electronics applications such as implantable electronics and flexible displays. Further, it will open new avenues for realizing multi-layered multi-material (foil-to-foil) integrated bendable electronics.
The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18-µm technology were fabricated in two separated chips. The two fabricated chips were thinned down to 20 µm using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch). Index Terms-CAD, CMOS, device modeling, flexible electronics, thinning-down techniques, ultrathin silicon. I. INTRODUCTION M ICROELECTRONICS has revolutionized our lives through fast communication and computing. Currently, the field is dominated by the silicon-based CMOS Manuscript
Device modelling for bendable piezoelectric FET-based touch sensing system.Abstract-Flexible electronics is rapidly evolving towards devices and circuits to enable numerous new applications. The high-performance, in terms of response speed, uniformity and reliability, remains a sticking point. The potential solutions for high-performance related challenges bring us back to the timetested silicon based electronics. However, the changes in the response of silicon based devices due to bending related stresses is a concern, especially because there are no suitable models to predict this behavior. This also makes the circuit design a difficult task. This paper reports advances in this direction, through our research on bendable Piezoelectric Oxide Semiconductor Field Effect Transistor (POSFET) based touch sensors. The analytical model of POSFET, complimented with Verilog-A model, is presented to describe the device behavior under normal force in planar and stressed conditions. Further, dynamic readout circuit compensation of POSFET devices have been analyzed and compared with similar arrangement to reduce the piezoresistive effect under tensile and compressive stresses. This approach introduces a first step towards the systematic modeling of stress induced changes in device response. This systematic study will help realize high-performance bendable microsystems with integrated sensors and readout circuitry on ultra-thin chips (UTCs) needed in various applications, in particular, the electronic skin (e-skin).
Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (I ON ) and OFF-current (I OFF ) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low-and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high I ON and low I OFF current. The impact of work function variations and doping on device performance is also comprehensively investigated.
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